2020
DOI: 10.1109/tvlsi.2020.3003091
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An Active Silicon Interposer With Low-Power Hybrid Wireless-Wired Clock Distribution Network for Many-Core Systems

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“…As each clock driver adds timing uncertainty, jitter (random variation in clock arrival time) and skew (spatial variation in clock arrival time) performances are also significantly impaired. As a result, both jitter and skew performances have been limited to several to tens ps range 1 , 5 , 8 , 10 . While the demand for higher data rates necessitates a tighter jitter and skew budget, clock skew and jitter deteriorate as on-chip process, voltage and temperature (PVT) variations worsen in deep sub-micron processes.…”
Section: Introductionmentioning
confidence: 99%
“…As each clock driver adds timing uncertainty, jitter (random variation in clock arrival time) and skew (spatial variation in clock arrival time) performances are also significantly impaired. As a result, both jitter and skew performances have been limited to several to tens ps range 1 , 5 , 8 , 10 . While the demand for higher data rates necessitates a tighter jitter and skew budget, clock skew and jitter deteriorate as on-chip process, voltage and temperature (PVT) variations worsen in deep sub-micron processes.…”
Section: Introductionmentioning
confidence: 99%