An accurate yield estimation approach for multivariate non-normal data in semiconductor quality analysis

Kovacs, Ingrid; Ţopa, Marina; Buzo, Andi; Pelz, Georg

doi:10.1109/smacd.2017.7981609

Cited by 8 publications

(3 citation statements)

References 10 publications

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“…[3], wafer yield estimation in Refs. [4], [5], probe yield excursion detection and root cause analysis in Ref. [6], probe yield analysis based on wafer spatial features in Refs.…”

Section: Related Workmentioning

confidence: 99%

A Gaussian Mixture Model Clustering Ensemble Regressor for Semiconductor Manufacturing Final Test Yield Prediction

2021

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In the semiconductor industry, many studies have been carried out for front-end related process improvement and yield prediction using machine learning techniques. However, very few research investigations have dealt with the backend Final Test (FT) yield prediction using the front-end wafer acceptance test (WAT) parameters. The manufacturing cycle time between wafer fabrication (WF) and FT can range anywhere between a few weeks to several months. It is therefore important for semiconductor manufacturers to detect wafer material related low yield problems at an earlier stage for effective cost and quality control. This is a challenging goal as the input data used for prediction is at a very early manufacturing stage and the output FT yield for packaged chips is the last stage of the fabrication chain. There are many unknown production variations caused by different manufacturing processes, equipment configurations and human interferences in this multi-stage sequential fabrication chain. In this paper, we proposed a novel procedure to predict the backend FT yield at the WF stage itself using a Gaussian Mixture Models (GMM) clustering approach that is applied to build a weighted ensemble regressor. Real production data for new chip product lines are verified with this method and show significant improvement in the prediction performance.

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“…[3], wafer yield estimation in Refs. [4], [5], probe yield excursion detection and root cause analysis in Ref. [6], probe yield analysis based on wafer spatial features in Refs.…”

Section: Related Workmentioning

confidence: 99%

A Gaussian Mixture Model Clustering Ensemble Regressor for Semiconductor Manufacturing Final Test Yield Prediction

2021

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“…However, because of the process variation exist, the manufactured ICs tend to exhibit different performances. The process variation is inherent and affects the IC quality and production costs and methods are needed to quantify its effect (Kovacs et al, 2017). Unit Yield is usually in percentage, and a typical product yield for CMOS ranges from 95% to 99% (Jones, 2010).…”

Section: Introductionmentioning

confidence: 99%

Salicide Residues Defects Characterization and Reduction in Front-End Pre-Metal Cleaning Process Wafer Fabrication

Johann

2022

etj

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Wafer fabrication for integrated circuit is one of the most complicated process in semiconductor manufacturing industry. High yield is always the ultimate goal to achieve hence a good defect management is the key to ensure the goal is met. Salicide residue is a major defect wet etching process. The defect is contributing a total of 1% loss in overall wafer fab sort yield, that is an equivalent to USD$ 5 million loss per year. The objective for this research is to identify the root cause and determine the element of the residue defect in the wafer substrate at Salicide Pre-Clean wafer fabrication process. Once this has been achieved, next is to determine a novelty solution to reduce the residue defects and finally validate the effectiveness of the novel solution in reducing the salicide residue defects. An investigation of one factor at the time has been conducted with various experiments including screening all the hardware resources available by using ANOVA studies. The result has concluded that the salicide residue consists of carbon defect is observed after Salicide Pre-Clean step when the standard diluted hydrofluoric acid (dHF) is used by the wet station equipment to clean the product wafers. This study has discovered an innovated solution to minimize the chemical contact on the wafer has resulted in reducing the post clean defects residue by 80% and eliminate 1% of the total product sort yield loss issue.

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“…Recent papers show an increasing interest in SSTA [6]- [9], and the need for fast algorithms for stochastic analysis has increased. For this reason, we first propose to initiate a new statistical approach that relies on an analytical treatment of one gate.…”

Section: Introductionmentioning

confidence: 99%

Statistical Simulations of Delay Propagation in Large Scale Circuits Using Graph Traversal and Kernel Function Decomposition

Freeley

Mishagli

Brazil

et al. 2018

2018 15th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (

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An accurate yield estimation approach for multivariate non-normal data in semiconductor quality analysis

Cited by 8 publications

References 10 publications

A Gaussian Mixture Model Clustering Ensemble Regressor for Semiconductor Manufacturing Final Test Yield Prediction

A Gaussian Mixture Model Clustering Ensemble Regressor for Semiconductor Manufacturing Final Test Yield Prediction

Salicide Residues Defects Characterization and Reduction in Front-End Pre-Metal Cleaning Process Wafer Fabrication

Statistical Simulations of Delay Propagation in Large Scale Circuits Using Graph Traversal and Kernel Function Decomposition

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