An accurate probabilistic model for error detection

Rejimon, T.; Bhanja, Sanjukta

doi:10.1109/icvd.2005.46

Cited by 24 publications

(10 citation statements)

References 18 publications

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“…The attractive feature of this graphical representation of the joint probability distribution is that not only does it make conditional dependency relationships among the nodes explicit but it also serves as a computational mechanism for efficient probabilistic updating. Bayesian networks have traditionally been used in medical diagnosis, artificial intelligence, image analysis, and specifically in switching model [2] and single stuck-at-fault/error model [5] in VLSI but their use in timing aware modeling of Single-Event-Upsets is new. We first explore an exact inference scheme also known as clustering technique [13], where the original DAG is transformed into special tree of cliques such that the total message passing between cliques will update the overall probability of the system.…”

Section: Ses J Q L R H P´seu J µP´t J I µP´q L T J I µmentioning

confidence: 99%

A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis

Rejimon

Bhanja

2006

IEEE Trans. VLSI Syst.

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Abstract-With device size shrinking and fast rising frequency ranges, effect of cosmic radiations and alpha particles known as Single-Event-Upset (SEU), Single-Event-transients (SET), is a growing concern in logic circuits. Accurate understanding and estimation of Single-Event-Upset sensitivities of individual nodes is necessary to achieve better soft error hardening techniques at logic level design abstraction. We propose a probabilistic framework to the study the effect of inputs, circuits structure and gate delays on Single-Event-Upset sensitivities of nodes in logic circuits as a single joint probability distribution function (pdf). To model the effect of timing, we consider signals at their possible arrival times as the random variables of interest. The underlying joint probability distribution function, consists of two components: ideal random variables without the effect of SEU and the random variables affected by the SEU. We use a Bayesian Network to represent the joint pdf which is a minimal compact directional graph for efficient probabilistic modeling of uncertainty. The attractive feature of this model is that not only does it use the conditional independence to arrive at a sparse structure, but also utilizes the same for smart probabilistic inference. We show that results with exact (exponential complexity) and approximate non-simulative stimulus-free inference (linear in number of nodes and samples) on benchmark circuits yield accurate estimates in reasonably small computation time.

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Section: Ses J Q L R H P´seu J µP´t J I µP´q L T J I µmentioning

confidence: 99%

A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis

Rejimon

Bhanja

2006

IEEE Trans. VLSI Syst.

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“…Symbolic analyses use formal methods to propagate probabilities through a symbolic representation of a circuit, e.g., a DAG-based netlist [4], a representation for Boolean functions [6], or a representation for probabilistic networks [3], [7], [8]. However, exact symbolic algorithms are difficult to scale in the presence of path re-convergence [2], [3], 1 and approximations introduced in practical implementations often produce large estimation errors [4] and have poor estimation of reliability compared to simulation-based approaches.…”

Section: Introductionmentioning

confidence: 99%

RALF: Reliability Analysis for Logic Faults — An exact algorithm and its applications

Luckenbill¹,

Lee²,

Yu³

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Reliability analysis for a logic circuit is one of the primary tasks in fault-tolerant logic synthesis. Given a fault model, it quantifies the impact of faults on the full-chip fault rate. We present RALF, an exact algorithm for calculating the reliability of a logic circuit. RALF is based on the compilation of a circuit to deterministic decomposable negation normal form (d-DNNF), a representation for Boolean formulas that can be more succinct than BDDs. Our algorithm can solve a large set of MCNC benchmark circuits within 5 minutes, enabling an optimality study of Monte Carlo simulation, a popular estimation method for reliability analysis, on real benchmark circuits. Our study shows that Monte Carlo simulation with a small set of random vectors generally has a high fidelity for the computation of full-chip fault rates and the criticality of single gates. While we focus on reliability analysis, RALF can also be used to efficiently locate random pattern resistant faults. This can be used to identify where methods other than random simulation should be used for accurate criticality calculations and where to enhance the testability of a circuit.

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“…It was then extended by [11][12] to handle multiple fault situations, however, they only consider stuck-at-faults. In [13] authors use Bayesian networks to calculate the output error probabilities without considering the input signal probabilities.…”

Section: Introductionmentioning

confidence: 99%

Probabilistic error propagation in logic circuits using the Boolean difference calculus

Mohyuddin

Pakbaznia

Pedram

2008

2008 IEEE International Conference on Computer Design

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-A gate level probabilistic error propagation model is presented which takes as input the Boolean function of the gate, the signal and error probabilities of the gate inputs, and the gate error probability and produces the error probability at the output of the gate. The presented model uses the Boolean difference calculus and can be applied to the problem of calculating the error probability at the primary outputs of a multi-level Boolean circuit with a time complexity which is linear in the number of gates in the circuit. This is done by starting from the primary inputs and moving toward the primary outputs by using a post-order traversal. Experimental results demonstrate the accuracy and efficiency of the proposed approach compared to the other known methods for error calculation in VLSI circuits.

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An accurate probabilistic model for error detection

Abstract: We

Cited by 24 publications

References 18 publications

A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis

A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis

RALF: Reliability Analysis for Logic Faults — An exact algorithm and its applications

Probabilistic error propagation in logic circuits using the Boolean difference calculus

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An accurate probabilistic model for error detection

Abstract: We

Cited by 24 publications

References 18 publications

A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis

A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis

RALF: Reliability Analysis for Logic Faults &#x2014; An exact algorithm and its applications

Probabilistic error propagation in logic circuits using the Boolean difference calculus

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RALF: Reliability Analysis for Logic Faults — An exact algorithm and its applications