An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations

Perez, Zahira; Villacorta, Hector; Champac, Victor

doi:10.1109/vlsi-soc.2018.8644864

Cited by 3 publications

(1 citation statement)

References 12 publications

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“…In order to obtain specialised information for steering statistical optimisation, characteristic metrics have been introduced [6, 13–35]. Yield gradient (YG) which is an effective sensitivity metric for guiding the statistical timing optimisation flow is defined as the change in the timing yield (TY) of the circuit for small changes in the size of the gates [19, 24].…”

Section: Introductionmentioning

confidence: 99%

Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuits

Ebrahimipour

Ghavami

Raji

2019

IET Circuits, Devices & Systems

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As CMOS devices become smaller, process variations-induced uncertainty imposes a large spread in the circuit timing and therefore, it becomes one of the main issues for circuit yield. To analyse/optimise the timing of the circuit under process variation effects, statistical analysis/optimisation techniques are more suitable than the traditional static analysis/ optimisation counterparts. Statistical gate sizing is an effective technique that is widely used to guide the timing yield improvement of digital circuits. Gate criticality, defined as the probability that a gate lies on a critical path, forms the basis for many of the existing statistical gate sizing techniques. Here, the authors introduce adjacency criticality to address the drawbacks of the conventional definition of gate criticality. It is defined as the probability of manufacturing a chip in which the gate lies on the critical path due to process variation considering the effect of the gates in its fan-out cone. Furthermore, the authors present the levelised Adjacency Criticality metric which provides a trade-off between the runtime of the criticality metric and accuracy of the Adjacency Criticality metric. In order to show the efficacy of the proposed metric, an adjacency criticalitybased statistical gate sizing method is presented for improving timing yield of the circuit.

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Section: Introductionmentioning

confidence: 99%

Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuits

Ebrahimipour

Ghavami

Raji

2019

IET Circuits, Devices & Systems

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Reliable Circuit Design Using a Fast Incremental-Based Gate Sizing Under Process Variation

Ghavami

Raji

Ibrami

et al. 2022

IEEE Trans. Device Mater. Relib.

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Gate Sizing Methodology with a Novel Accurate Metric to Improve Circuit Timing Performance under Process Variations

2020

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The impact of process variations on circuit performance has become more critical with the technological scaling, and the increasing level of integration of integrated circuits. The degradation of the performance of the circuit means economic losses. In this paper, we propose an efficient statistical gate-sizing methodology for improving circuit speed in the presence of independent intra-die process variations. A path selection method, a heuristic, two coarse selection metrics, and one fine selection metric are part of the new proposed methodology. The fine metric includes essential concepts like the derivative of the standard deviation of delay, a path segment analysis, the criticality, the slack-time, and area. The proposed new methodology is applied to ISCAS Benchmark circuits. The average percentage of optimization in the delay is 12%, the average percentage of optimization in the delay standard deviation is 27.8%, the average percentage in the area increase is less than 5%, and computing time is up to ten times less than using analytical methods like Lagrange Multipliers.

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An accurate novel gate-sizing metric to optimize circuit performance under local intra-die process variations

Cited by 3 publications

References 12 publications

Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuits

Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuits

Reliable Circuit Design Using a Fast Incremental-Based Gate Sizing Under Process Variation

Gate Sizing Methodology with a Novel Accurate Metric to Improve Circuit Timing Performance under Process Variations

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