An Accurate Drain Current Model of Dual Material Double Gate Metal Oxide Semiconductor Field Effect Transistor

Chakrabarti, Himeli; Maity, Reshmi; Baishya, Srimanta; Maity, N. P.

doi:10.1007/s12633-021-01321-y

Cited by 3 publications

(1 citation statement)

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“…In this scenario, the quantum mechanical (QM) phenomenon takes place, and as a result of this quantization phenomenon, the threshold voltage of the device increases [3]- [7]. Another design used to address the short channel effect (SCE) problems is the double gate (DG) MOSFET architecture [8]. It is because by raising the number of gates in the channel, the electrostatic regulation of the channel is improved, and the short-channel effects are decreased.…”

Section: Introductionmentioning

confidence: 99%

Optimization of 14 nm double gate Bi-GFET for lower leakage current

Nizam

Hamid²,

Salehuddin³

et al. 2023

TELKOMNIKA

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In recent years, breakthroughs in electronics technology have upgraded the physical properties of the metal oxide semiconductor field effect transistor (MOSFET) toward smaller sizes and improvements in both quality and performance. Hence, the growth field effect transistor (GFET) is being promoted as one of the worthy candidates due to its superior material characteristics. A 14 nm horizontal double-gate bilayer graphene field effect transistor (FET) utilizing high-k and a metal gate, which are composed of hafnium dioxide (HfO2) and tungsten silicide (WSix) respectively. Silvaco ATHENA and ATLAS technology computer-aided design (TCAD) tools are used to simulate the design and electrical properties, while Taguchi L9 orthogonal arrays (OA) are used to optimize the electrical properties. The threshold voltage (VTH) adjustment implant dose, VTH adjustment implant energy, source/drain (S/D) implant dose, and S/D implant energy have all been investigated as process parameters, while the VTH adjustment tilt angle and the S/D implant tilt angle have been investigated as noise factors. When compared to the initial findings before optimization, the IOFF has a value of 29.579 nA/µm, indicating a significant improvement. Findings from the optimization technique demonstrate excellent device performance with an IOFF of 28.564 nA/µm, which is closer to the international technology roadmap for semiconductors (ITRS) 2013 target.

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Section: Introductionmentioning

confidence: 99%