The demands for a high-density, high-speed, and smaller integrated circuit have resulted in 3D stacked packages with through-silicon via (TSV) technology. Due to their sophisticated structure and complex manufacturing process, however, many issues related to the reliability and thermal management of these 3D packages are still under investigation. Failure at the solder joints between the chip and substrate is inevitable when the 3D package is exposed to thermal loading. The discrepancy in the coefficients of thermal expansion (CTE) between the chip and substrate subjects the solder joints to significant stress and strain. To reduce these thermally induced stresses and strains, an underfill has been used. The optimization of this underfill material is thus one of the most critical issues in improving the reliability and thermal performance of 3D packages. This paper describes a parametric study based on computational fluid dynamics (CFD) analysis to address the junction temperature of the package. The impact on the package temperature of various factors such as the thermal conductivity of underfill, mold compound, substrate, and copper bump ratio was investigated. In addition, the transient heat transfer coefficients from CFD analysis were extracted and used as a thermal boundary condition in thermal and structural finite element analysis (FEA). In thermal and structural simulation, the strain energy at the solder joint was compared by changing the material properties of the underfill. The modulus, CTE, and glass transition temperature (T g ) of the underfill were examined. The most effective material properties were adopted to minimize modeling complexity and reduce computing time. The results of this work should help to design more reliable 3D packages.
IntroductionThe microelectronics industry is focusing on achieving a high-speed, high-function, and reduced power-consumption integrated circuit in a smaller package. As a result, 3D packaging is gaining popularity. However, the advantages of multi-chip stacking cannot be fully used by wire-bonding technology since the number of I/O pads on the chip has increased significantly. Thus, TSV technology has become an attractive option to achieve 3D packaging. 3D packages with TSV technology have not yet matured and, many challenges related to manufacturing processes, reliability, and thermal management still must be addressed. In particular, due to the vertically stacked structure of 3D packages, thermal management is the most critical concern. The heat flux generation by multi-stacked chips in one small package is