An accelerated successive approximation technique for analog to digital converter design

Wang, Haibo; Radhakrishnan, Ram Harshvardhan

doi:10.1109/socc.2014.6948934

Cited by 2 publications

(1 citation statement)

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“…Measurements also demonstrate the potentials of using information extracted from VCDL intermediate stages to improve the ADC signal-to-noise distortion ratio (SNDR). A preliminary work related to the proposed techniques was published in [27]. The significant differences between this work and [27] include: (i) techniques to adaptively select intermediate stage signals are developed in this work and (ii) silicon design and measurement results are presented to validate the proposed techniques in this work.…”

Section: Introductionmentioning

confidence: 99%

Exploiting uncertain timing information in time‐based SAR ADCs

Wang

Nagabhushana

Leitner

2020

IET Circuits, Devices & Systems

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Time-based successive approximation register (SAR) analogue-to-digital converters (ADCs) are gaining attraction in ultra-low voltage circuit design. Such ADCs typically use multi-stage voltage controlled delay lines (VCDLs) to perform voltage to time conversion in order to mitigate limited headroom of voltage signals. Although multi-stage VCDLs are used, only the outputs of the final VCDL stages are compared during bit trials. This work demonstrates that additional bit information can be extracted by scavenging timing information revealed at VCDL intermediate stages. The additional bit information can be used to accelerate the ADC conversion process or improve signal-to-noise distortion ratio (SNDR). To cope with uncertainties associated with signals from VCDL intermediate stages, an uncertainty-tolerant SAR procedure is developed. Also, this work presents techniques for adaptively selecting which intermediate stage signals to be tapped along the conversion process. The proposed techniques are applied in the design of a 0.4 V 9-bit SAR ADC in a 130 nm CMOS technology. Silicon measurement results show that with the additional information extracted from VCDL intermediate stages the conversion for the vast majority of ADC inputs can be completed in 7 or 8 clock cycles. Measurement results also demonstrate the potentials of using the intermediate stage signals to improve ADC SNDR.

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Section: Introductionmentioning

confidence: 99%