An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane

Fukuda, K.; Yamashita, Hiroyuki; Yuki, Fumio; Yagyu, Masayoshi; Nemoto, Ryo; Tokuda, Takashi; Saito, Tatsuya; Chujo, Norio; Yamamoto, Keiichi; Kanai, Hiroyuki; Hayashi, Atsushi

doi:10.1109/isscc.2008.4523075

Cited by 18 publications

(11 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Conventionally, electrical transmissions have been applied up to 10 Gb/s per channel. The power efficiency, energy per bit stream, has been in the order of 30-60 mW/Gb/s, and recently, it has been improved to 25 mW/Gb/s for 100 cm transmission at the data rate of 8 Gb/s [2]. However, the efficiency is significantly degraded beyond 10 Gb/s, because of serious bandwidth limitation caused by skin effect.…”

Section: Introductionmentioning

confidence: 99%

A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS

Tokuda

Yuki

Yamashita

et al. 2010

IEEE Custom Integrated Circuits Conference 2010

View full text Add to dashboard Cite

A 25 Gb/s × 4-channel transimpedance amplifier has been realized in 65-nm CMOS technology. It achieves transimpedance gain of 69.8 dBȍ, bandwidth of 22.8 GHz, and gains flatness of under ±2 dB after equalizing the effect of transmission loss, incorporating gain-stage amplifier with flat frequency response, and 50ȍ-output driver with an analogue equalizer. The proposed TIA dissipates only 74 mW/ch and demonstrates the transimpedance bandwidth products per DC power of 952.1 GHzȍ/mW and crosstalk of less than -17 dB. The sensitivity at bit error rate (BER) of less than 10 -12 was measured to be the optical input power of -7.4 dBm for multi-channel operation at the data rate of 25 Gb/s, and also demonstrates only 0.8 dB power penalty.

show abstract

Section: Introductionmentioning

confidence: 99%

A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS

Tokuda

Yuki

Yamashita

et al. 2010

IEEE Custom Integrated Circuits Conference 2010

View full text Add to dashboard Cite

show abstract

“…In such pre-emphasis schemes, delayed copies of the symbols are weighted and summed to create equalizing finite impulse response (FIR) filters [97,98,[111][112][113][114][115][116][117].…”

Section: Transmitter-side Equalizationmentioning

confidence: 99%

“…But DFE with more than a few taps tends to become complex and power hungry, so it is sometimes combined with a linear equalizer [111,112,116,137,138]. An often stated motivation is that linear equalizers can cancel long tails in the symbol response with lower complexity.…”

Section: Receiver-side Equalizationmentioning

confidence: 99%

“…This is especially so when loop-unrolling (see section 7.6) is used, because then there is no single stable transition point for a phase-detector to use, as discussed in [116,138]. So for many receivers with loop-unrolled DFE, the CDR is a standalone circuit that primarily uses the input signal to the DFE for phase detection [100,111,114], possibly also taking some information from the DFE output into account [135,141].…”

Section: Adaptive Equalization and Clock Recoverymentioning

confidence: 99%

“…Some receivers with loop-unrolled DFE manage to do this by using more complex phase detectors than the classical Hogge or Alexander detectors, using for example multiple edge detectors with different thresholds (an 'unrolled' edge detector) [115] or an 'eye tracking' phase-detector that does not sample on the edge but just before and after it [116].…”

Section: Adaptive Equalization and Clock Recoverymentioning

confidence: 99%

See 2 more Smart Citations