An 847–955 Mb/s 342–397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 $\mu$m CMOS

Xiang, Bo; Bao, Dan; Huang, Shuangqu; Zeng, Xiaoyang

doi:10.1109/jssc.2011.2125030

Cited by 39 publications

(32 citation statements)

References 27 publications

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“…Hyeong-Ju Kang and Byung-Do Yang  This property has been exploited by the pre-rotator structure and the rotator-in-series structure [3], [7].…”

Section: Low-complexity Multi-size Cyclic-shifter For Qc-ldpc Codesmentioning

confidence: 99%

“…1. Previous structures: (a) pre-rotator and MUX-network structure [3], (b) rotator-in-parallel structure [6], (c) rotator-in-series structure [7], and (d) Benes-network structure [9]. …”

Section: Multi-size Cyclic Shiftermentioning

confidence: 99%

“…The results of the barrel rotators are then combined by MUXs to become the output data. In the rotator-in-series structure, the first barrel rotator rotates the input data by s, and the second one rotates the result of the first one in the same direction by N -z [7]. The output data are also selected from the barrel rotator outputs.…”

Section: Prerotationmentioning

confidence: 99%

“…The previous structures are compared in Table 1 for N = 3 × 2 n and GCD g = 2 m . In the first column, MN, RIP, RIS, BN, and F3 are the MUX-network structure of [3], the rotator-inparallel structure of [6], the rotator-in-series structure of [7], the Benes-network structure of [9], and the Benes-network structure with the fast 3 × 3 switch of [12], respectively. The number of MUXs, shown in the second column, is normalized by Nw, and the delay in the third column is normalized by T MUX .…”

Section: Prerotationmentioning

confidence: 99%

“…Another kind of MSCS structure is based on normal barrel rotators. To support various sizes, two barrel rotators are placed in parallel [4], [6] or series [7]. The other kind is based on a Benes network, which can route any N × N permutation [8], [9].…”

Section: Introductionmentioning

confidence: 99%

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Low-Complexity Multi-size Cyclic-Shifter for QC-LDPC Codes

Kang

Yang

2017

ETRI Journal

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The decoding process of a quasi-cyclic low-density parity check code requires a unique type of rotator. These rotators, called multi-size cyclic-shifters (MSCSs), rotate input data with various sizes, where the size is the amount of data to be rotated. This paper proposes a lowcomplexity MSCS structure for the case when the sizes have a nontrivial common divisor. By combining the strong points of two previous structures, the proposed structure achieves the smallest area. The experimental results show that the area reduction was more than 14.7% when the proposed structure was applied to IEEE 802.16e as an example.

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“…Hyeong-Ju Kang and Byung-Do Yang  This property has been exploited by the pre-rotator structure and the rotator-in-series structure [3], [7].…”

Section: Low-complexity Multi-size Cyclic-shifter For Qc-ldpc Codesmentioning

confidence: 99%

“…1. Previous structures: (a) pre-rotator and MUX-network structure [3], (b) rotator-in-parallel structure [6], (c) rotator-in-series structure [7], and (d) Benes-network structure [9]. …”

Section: Multi-size Cyclic Shiftermentioning

confidence: 99%

Section: Prerotationmentioning

confidence: 99%

Section: Prerotationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low-Complexity Multi-size Cyclic-Shifter for QC-LDPC Codes

Kang

Yang

2017

ETRI Journal

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Certain investigations on recent advances in the design of decoding algorithms using low‐density parity‐check codes and its applications

Roberts¹,

Kumari

Anguraj³

2021

Int J Communication

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Summary Information theory coding is an impressive and most celebrated field of research that has spawned numerous extremely important solutions to the intractable problems of secure data communications. Recent advancements in error control coding methods have seen a huge surge in using low‐density parity‐check (LDPC) code‐based decoding algorithms to solve imperative issues related to reliable data transmission and reception. Till date, extensive research efforts have been consistently being made on LDPC codes which focus on algorithm‐driven and hardware‐realization‐based approaches. The main intension of this research work is to provide an extensive systematic elucidation on the recent advancements in LDPC decoding algorithms. In addition, a thorough performance evaluation and analysis of several outstanding LDPC decoding techniques is presented. Finally, conclusions are drawn by summarizing the important research findings, interesting open problems, current challenges and broader perspectives for future directions of research.

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FPGA-Based High Throughput TDMP LDPC Decoder

Liao

Liu

2016

Communications in Computer and Information Science

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Abstract. In this paper, a high-throughput decoder architecture for quasi-cyclic low density parity check (QC-LDPC) codes is presented. Using the Normalized Min-Sum algorithm and the turbo-decoding message-passing algorithm, the proposed design expanded degree of parallelism to improve the throughput at a cost of hardware resource usage. Based on the proposed architecture, we implemented a (8176, 7154) Euclidian geometry-based QC-LDPC code decoder on a Xilinx Kintex7 (XC7K325T-2) board. The FPGA implementation results show that the decoder can achieve a total decoding throughput of 1.6 Gbps at the clock frequency of 105Mth at 10 iterations.

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An 847–955 Mb/s 342–397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 $\mu$m CMOS

Cited by 39 publications

References 27 publications

Low-Complexity Multi-size Cyclic-Shifter for QC-LDPC Codes

Low-Complexity Multi-size Cyclic-Shifter for QC-LDPC Codes

Certain investigations on recent advances in the design of decoding algorithms using low‐density parity‐check codes and its applications

FPGA-Based High Throughput TDMP LDPC Decoder

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