An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

Bae, Seung-Jun; Park, Kwang-Il; Ihm, Jeong-Don; Song, Hoyoung; Lee, Woojin; Kim, Hyun‐Jin; Kim, Kyoungho; Park, Yoon-Sik; Park, Min Sang; Lee, Hong-Kyong; Bang, Sam-Young; Moon, Gil-Shin; Hwang, Seok-Won; Cho, Youngchul; Hwang, Sang-Jun; Kim, Dae-Hyun; Lim, Jeong-Ok; Kim, Jae-Sung; Kim, Sung Hoon; Jang, Seong-Jin; Choi, Jongwan; Jun, Young-Hyun; Kim, Kinam; Cho, Soo-In

doi:10.1109/jssc.2007.908002

Cited by 55 publications

(18 citation statements)

References 14 publications

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“…However, the challenge is in knowing the correct timing compensation, which is also dependent on the process variation [10]. Crosstalk in the memory interface has also been addressed by Bae et al [11], where it limits the maximum number of transitioning lanes, but does not compensate for the distorted signals. Other approaches to compensate for crosstalk noise include the use of staggered I/Os combined with a glitch suppression scheme to improve vertical eye opening or a slew rate control driver on transmitter (TX).…”

Section: Introductionmentioning

confidence: 99%

An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels

Aprile

Cevrero

Francese

et al. 2018

IEEE J. Solid-State Circuits

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Section: Introductionmentioning

confidence: 99%

An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels

Aprile

Cevrero

Francese

et al. 2018

IEEE J. Solid-State Circuits

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“…The outputs of DBI DC encoder have 5 case of the number of '0'. The minimum number of zeros is 0 and the maximum number of zeros is 4 [2].…”

Section: Introductionmentioning

confidence: 99%

A high speed graphics DRAM with low power and low noise data bus inversion in 54nm CMOS

Kwack

2009

IEICE Electron. Express

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This paper presents a high speed 1 Gb GDDR3 Graphics DRAM using data bus inversion (DBI) DC mode in order to achieve low power and low noise in DRAM. A DBI, digital majority voter (DMV) circuit and the Global I/O (GIO) control circuit on the DBI DC mode are newly proposed. In this DMV, The current of GIO toggle pattern is consumed less than 47% compared with the analog majority voter (AMV). The voltage fluctuation wave form of the data eye is also reduced in accordance with DBI on the operation mode. Using the proposed DBI scheme can produce almost stable signal integrity of the DQs against high speed operation. The DBI is fabricated using 54 nm technology.

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confidence: 99%

“…However, reference signal (V ref ) noise reduces the noise margin of receiver input signals [1]. Several works are reported to solve the problems owing to reference signal noise [1][2][3][4]. However, in [1,2], simultaneous switching noise (SSN) is not completely removed and a reference voltage offset also exists.…”

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confidence: 99%

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Three-level differential buffer for increasing noise margin in pseudo-differential signalling

Kim

Bae

et al. 2010

Electron. Lett.

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A 5Gbit/s/pin transceiver for high-speed memory interfaces is implemented in a 0.18 mm CMOS process. In general, memory interfaces use single-ended signalling with a reference signal because the chip cost is closely related to the number of pins. However, as the data rate increases, reference voltage noise and simultaneous switching noise reduce voltage and timing margin of receiver input signals. Pseudo-differential signalling (PDS) is used to solve the problems, however a previous receiver using PDS is sensitive to core power noise because the receiver uses three-level signals with reduced noise margin. The three-level differential buffer (TLDB) which is robust to core power noise is proposed and the noise margin of the TLDB outputs is larger than that of outputs of a previous PDS receiver.

show abstract

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

Cited by 55 publications

References 14 publications

An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels

An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels

A high speed graphics DRAM with low power and low noise data bus inversion in 54nm CMOS

Three-level differential buffer for increasing noise margin in pseudo-differential signalling

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