An 8-Channel Scalable EEG Acquisition SoC With Patient-Specific Seizure Classification and Recording Processor

Yoo, Jerald; Yan, Lei; El-Damak, Dina; Altaf, Muhammad Awais Bin; Shoeb, Ali; Chandrakasan, Anantha P.

doi:10.1109/jssc.2012.2221220

Cited by 240 publications

(102 citation statements)

References 14 publications

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“…2. There are examples showing a wide range of boosted impedance from 30MOhm [14] to 500MOhm [8], because the optimum value of C3 is rather difficult to control at implementation level, as discussed in section III.A. It is worth noting that the positive feedback technique can also be used in the proposed resistive feedback amplifier to boost the input impedance, if the application requirements demand very large input impedance.…”

Section: B Benchmarking and Discussionmentioning

confidence: 99%

“…The input voltage creates a signal current through Rin, which is copied to Ro and defines the output voltage. To obtain the high-pass corner frequency, a current-based DC servo loop is applied to null the DC current in presence of differential electrode offset (VDEO) by tuning I7, 8. Since now Zin is determined by Camp, the value of C1 can be made large to reduce the ratio Camp/C1 without compromising Zin.…”

Section: A Resistive Feedback Vs Capacitive Feedbackmentioning

confidence: 99%

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A Noise Reconfigurable Current-Reuse Resistive Feedback Amplifier with Signal Dependent Power Consumption for Fetal ECG Monitoring

et al. 2016

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• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication Citation for published version (APA):Song, S., Rooijakkers, M. J., Harpe, P., Rabotti, C., Mischi, M., Van Roermund, A. H. M., & Cantatore, E. (2016). A noise reconfigurable current-reuse resistive feedback amplifier with signal-dependent power consumption for fetal ECG monitoring. IEEE Sensors Journal, 16(23),[8304][8305][8306][8307][8308][8309][8310][8311][8312][8313]. DOI: 10.1109/JSEN.2016 General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Abstract-This paper presents a noise-reconfigurable resistive feedback amplifier with current-reuse technique for fetal ECG monitoring. The proposed amplifier allows for both tuning of the noise level and changing the power consumption according to the signal properties, minimizing the total power consumption while satisfying all application requirements. The amplifier together with its amplitude detector and dynamical biasing circuit are implemented in a standard 0.18µm CMOS process. Measurements demonstrate that the proposed current-reuse resistive feedback topology improves the power efficiency of the conventional resistive feedback amplifier, achieving at the same time a good noise efficiency factor (NEF=2.8) and an input impedance of 20MOhm. The amplitude detector and dynamical biasing circuit, which tunes the current in the amplifier according to the signal amplitude, save up to 40% of the total power consumption. The amplifier achieves a measured noise level of 0.34µVrms in a 0.6 to 175Hz band, consuming 6.3µW power.

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Section: B Benchmarking and Discussionmentioning

confidence: 99%

Section: A Resistive Feedback Vs Capacitive Feedbackmentioning

confidence: 99%

A Noise Reconfigurable Current-Reuse Resistive Feedback Amplifier with Signal Dependent Power Consumption for Fetal ECG Monitoring

et al. 2016

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“…Similarly focusing on classifiers, while there has been recent work on low power implementations of Support Vector Machines (SVMs) (e.g. [15]), many current wearable algorithms are based on threshold detection. The wide range of machine learning approaches have not yet been explored.…”

Section: Gaps In the Signal Processing Landscapementioning

confidence: 99%

Opportunities and challenges for ultra low power signal processing in wearable healthcare

Casson

2015

2015 23rd European Signal Processing Conference (EUSIPCO)

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Wearable devices are starting to revolutionise healthcare by allowing the unobtrusive and long term monitoring of a range of body parameters. Embedding more advanced signal processing algorithms into the wearable itself can: reduce system power consumption; increase device functionality; and enable closed-loop recording-stimulation with minimal latency; amongst other benefits. The design challenge is in realising algorithms within the very limited power budgets available. Wearable algorithms are now emerging to answer this challenge. Using a new review, and examples from a case study on EEG analysis, this article overviews the state-of-the-art in wearable algorithms. It demonstrates the opportunities and challenges, highlighting the open challenge of performance assessment and measuring variability.

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“…If the algorithm determines that the incoming signal is abnormal, then the ASIC sends an alert signal and calls for help through wireless portable devices via the IoT. In such a system, the major challenges are the relatively large circuit area and high power of the DSP circuits performing multiply-and-accumulate (MAC) operations [5], which are adders and coefficient multipliers in digital filters. In order to miniaturize the physical size and extend the battery life of the circuits, low-complexity low-power designs are very important.…”

Section: Introductionmentioning

confidence: 99%

“…In order to miniaturize the physical size and extend the battery life of the circuits, low-complexity low-power designs are very important. As an example, in [5], an eight-channel 10-bit resolution DSP seizure detector processor consumes more than 50% of the chip area and power in a 5 mm × 5 mm system-on-a-chip (SOC) implemented in a 65-nm process, even though a look-up table (LUT) method is applied, which saved more than 50% of the total gate count in the digital filters [6]. Besides circuit complexity and power consumption, such circuits demand higher resolution and reliability, since higher resolution improves accuracy, and reliability is the key issue in biomedical applications.…”

Section: Introductionmentioning

confidence: 99%

Hardware-Efficient Delta Sigma-Based Digital Signal Processing Circuits for the Internet-of-Things

Liu

Furth

Tang

2015

JLPEA

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This paper presents hardware-efficient Delta Sigma linear processing circuits for the next generation low-power VLSI devices in the Internet-of-things (IoT). We first propose the P-N (positive-negative) pair method to manipulate both the analog value and length of a first-order Delta Sigma bit sequence. We then present a binary counter method. Based on these methods, we develop Delta Sigma domain on-the-fly digital signal-processing circuits: the Delta Sigma sum adder, average adder and coefficient multiplier. The counter-based average adder can work with both first-order and higher-order Delta Sigma modulators and can also be used as a coefficient multiplier. The functionalities of the proposed circuits are verified by MATLAB simulation and FPGA implementation. We also compare the area and power between the proposed Delta Sigma adders and a conventional multi-bit adder by synthesizing both circuits in the IBM 0.18-µm technology. Synthesis results show that the proposed Delta Sigma processing circuits can extensively reduce circuit area and power. With 100 inputs, a Delta Sigma average adder saves 94% of the silicon area and 96% of the power compared to a multi-bit binary adder. The proposed circuits have the potential to be widely used in future IoT circuits.

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An 8-Channel Scalable EEG Acquisition SoC With Patient-Specific Seizure Classification and Recording Processor

Cited by 240 publications

References 14 publications

A Noise Reconfigurable Current-Reuse Resistive Feedback Amplifier with Signal Dependent Power Consumption for Fetal ECG Monitoring

A Noise Reconfigurable Current-Reuse Resistive Feedback Amplifier with Signal Dependent Power Consumption for Fetal ECG Monitoring

Opportunities and challenges for ultra low power signal processing in wearable healthcare

Hardware-Efficient Delta Sigma-Based Digital Signal Processing Circuits for the Internet-of-Things

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