2012
DOI: 10.5194/ars-10-201-2012
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An 8 bit current steering DAC for offset compensation purposes in sensor arrays

Abstract: Abstract. An 8 bit segmented current steering DAC is presented for the compensation of mismatch of sensors with current output arranged in a large arrays. The DAC is implemented in a 1.8 V supply voltage 180 nm standard CMOS technology. Post layout simulations reveal that the design target concerning a sampling frequency of 2.6 MHz is exceeded, worst-case settling time equals 60.6 ns. The output current range is 0–10 μA, which translates into an LSB of 40 nA. Good linearity is achieved, INL < 0.5 LSB and DN… Show more

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Cited by 4 publications
(4 citation statements)
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References 14 publications
(18 reference statements)
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“…It is known from [6] that DACs in a sensor-actuator system do not need to have high-level performance in terms of speed, accuracy and linearity. Conversion speed of a few tens kilohertz and resolution of 6 to 8 bit are satisfactory in DACs for this application [6], [7]. DNL of less than 1 LSB (Least Significant Bit) is also good enough.…”
Section: Introductionmentioning
confidence: 88%
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“…It is known from [6] that DACs in a sensor-actuator system do not need to have high-level performance in terms of speed, accuracy and linearity. Conversion speed of a few tens kilohertz and resolution of 6 to 8 bit are satisfactory in DACs for this application [6], [7]. DNL of less than 1 LSB (Least Significant Bit) is also good enough.…”
Section: Introductionmentioning
confidence: 88%
“…Performance comparison with recently published 8-bit [7], 10-bit [8] and 12-bit converters [9]- [11] is given in Table 3. The proposed CS-DAC has the maximum data rate of 5 MS/s, while the recently published 12-bit converters report the maximum data rates of a few hundred MSample/s.…”
Section: Performance Comparisionmentioning
confidence: 99%
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