An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques

Paik, Daehwa; Asada, Yusuke; Miyahara, Masaya; Matsuzawa, Akira

doi:10.1587/transfun.e93.a.402

Cited by 5 publications

(8 citation statements)

References 14 publications

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“…This is because, in terms of I DS , a signal proportion of small V eff is larger than one of large V eff as shown in Fig. 8 [10]. As this ratio is large -or V eff is small -, integration time relatively becomes long.…”

Section: Gain Of Dynamic Amplifiermentioning

confidence: 94%

“…t 2 is decided as calculated results are close to simulation results and the time is set as 17 ps in this paper. Without this variable, the estimation is very different from simulation results as shown in reference [10]. Assuming an inverter chain of the second stage enters unstable equilibrium after (t 1 + t 2 ), t 3 is expressed as below [17], [18];…”

Section: Regeneration Timementioning

confidence: 96%

“…Equation 1shows that when there is mismatch due to input transistors, I DS changes from the designed value and the output of a pre-amplifier also varies from the ideal value. To compensate the mismatch, calibration of load capacitance [4], [5] and bypass current [9], [10] has been commonly selected. In the following sections, we will discuss the characteristic of each calibration method.…”

Section: Mismatchmentioning

confidence: 99%

“…However, both comparators suffer kick-back noise. To suppress the kick-back noise, in 2010, a pseudo-differential topology was introduced [10].…”

Section: Introductionmentioning

confidence: 99%

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An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator

Paik

Miyahara

Matsuzawa

2012

IEICE Trans. Fundamentals

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This paper analyzes a pseudo-differential dynamic comparator with a dynamic pre-amplifier. The transient gain of a dynamic preamplifier is derived and applied to equations of the thermal noise and the regeneration time of a comparator. This analysis enhances understanding of the roles of transistor's parameters in pre-amplifier's gain. Based on the calculated gain, two calibration methods are also analyzed. One is calibration of a load capacitance and the other is calibration of a bypass current. The analysis helps designers' estimation for the accuracy of calibration, dead-zone of a comparator with a calibration circuit, and the influence of PVT variation. The analyzed comparator uses 90-nm CMOS technology as an example and each estimation is compared with simulation results.

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Section: Gain Of Dynamic Amplifiermentioning

confidence: 94%

Section: Regeneration Timementioning

confidence: 96%