An 8-bit 120-MS/s Interleaved CMOS Pipeline ADC Based on MOS Parametric Amplification

Oliveira, João P.; Goes, J.; Figueiredo, Mauro; Santin, E.; Fernandes, Jorge; Ferreira, José Carlos

doi:10.1109/tcsii.2009.2038632

Cited by 14 publications

(4 citation statements)

References 11 publications

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“…The first difference of the MOSCAP structure proposed in [12] from the original structure in [13] is that two half-sized MOSCAPs are used in parallel rather than a single MOSCAP and with one pair of terminals left floating. The division into more than two devices can be used for higher unit capacitance values.…”

Section: Parametric Amplificationmentioning

confidence: 99%

“…4 Pseudo-differential dynamic source-follower 1.5-bit pipeline stage [11] Fig. 5 MOS parametric amplifier using two separated devices with a floating terminal [12] achievable gain also depends on the CM level of the input voltage, reflecting how well the MOS device is biased in the inversion region during the sampling phase. Therefore, an appropriate DC level has to be carefully chosen.…”

Section: Parametric Amplificationmentioning

confidence: 99%

See 1 more Smart Citation

Low-Power, High-Speed and High-Effective Resolution Pipeline Analog-to-Digital Converters in Deep Nanoscale CMOS

Goes

Pereira

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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This chapter reviews recent advances in low-power design techniques for high-speed and high-effective resolution pipeline Analog-to-Digital Converters (ADCs). The advantages of replacing, in a pipeline ADC architecture, the traditional local low-resolution parallel (flash) quantizers by low-resolution successiveapproximation register (SAR) ADCs are shown through a set of selected works. Some of the most promising energy-efficient residue amplification techniques are reviewed, spanning from open-loop and closed-loop amplifierless approaches to innovative and highly-scalable amplifier-based topologies.

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Section: Parametric Amplificationmentioning

confidence: 99%

Section: Parametric Amplificationmentioning

confidence: 99%

Low-Power, High-Speed and High-Effective Resolution Pipeline Analog-to-Digital Converters in Deep Nanoscale CMOS

Goes

Pereira

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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“…But other possibilities have been described. Reference [94] discloses an implementation based on parametric amplifiers, which consists of manipulating the inversion layer of MOS transistors to achieve voltage amplification [95,96]. This amplification mechanism is noise free, but highly dependent on parasitic capacitances, and not easy to implement with low supply voltages.…”

Section: Adcs With Residue Amplificationmentioning

confidence: 99%

Recent Advances and Trends in High-Performance Embedded Data Converters

Figueiredo¹

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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This chapter discusses the architectures of Nyquist rate Analog-toDigital Converters (ADCs), that are embedded in systems-on-chip (SoCs) implementing some of the most widespread mobile communication, wireless and wireline connectivity standards. The typical requirements for these ADCs are presented, and the main conversion architectures are described in terms of the fundamental operations realized inside them. This constitutes a unified treatment that relates all architectures, thus providing a deeper understanding of their fundamental limitations and trade-offs. We then discuss some of the solutions recently published in the literature to improve ADC energy efficiency. Finally we disclose implementation details from two 12 bit digitally calibrated, high-speed ADCs, using the pipeline and SAR architectures.

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“…The time-interleaved pipeline architecture is frequently used to satisfy the previous requirements in high speed, moderate resolution applications [1][2][3]. Its main advantage is the flexibility, hence different number of time-interleaved branches and pipeline stages can be enabled/disabled to configure variable resolution and sampling frequency, thus leading to a reconfigurable system.…”

Section: Introductionmentioning

confidence: 99%

An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H

Carvajal

Noije

2012

International Journal of Reconfigurable Computing

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This paper presents a 6 bit, 11 MS/s time-interleaved pipeline A/D converter design. The specification process, from block level to elementary circuits, is gradually covered to draw a design methodology. Both power consumption and mismatch between the parallel chain elements are intended to be reduced by using some techniques such as double and bottom-plate sampling, fully differential circuits, RSD digital correction, and geometric programming (GP) optimization of the elementary analog circuits (OTAs and comparators) design. Prelayout simulations of the complete ADC are presented to characterize the designed converter, which consumes 12 mW while sampling a 500 kHz input signal. Moreover, the block inside the ADC with the most stringent requirements in power, speed, and precision was sent to fabrication in a CMOS 0.35 μm AMS technology, and some postlayout results are shown.

show abstract

An 8-bit 120-MS/s Interleaved CMOS Pipeline ADC Based on MOS Parametric Amplification

Cited by 14 publications

References 11 publications

Low-Power, High-Speed and High-Effective Resolution Pipeline Analog-to-Digital Converters in Deep Nanoscale CMOS

Low-Power, High-Speed and High-Effective Resolution Pipeline Analog-to-Digital Converters in Deep Nanoscale CMOS

Recent Advances and Trends in High-Performance Embedded Data Converters

An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H

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