An 8 bit, 100 ms/s flash ADC

FAST AND POWER-EFFICIENT CMOS SUBRANGING ADCs

“…However, this requires the errors made by the CADC to be smaller than one least significant bit (LSB) of the FADC (LSB FADC ). 1 It is not possible to accomplish this without excessive power consumption inside the CADC. It is, therefore, com-techniques to increase the maximum clock speed without increasing the power consumption.…”

“…Several ADC architectures are capable of achieving these specifications, e.g. flash ADCs [1], pipeline ADCs [2][3][4], folding ADCs [5][6][7][8][9] and subranging ADCs [10][11][12]. However, when small die area, low-power and low-voltage operation are of primary importance, the two-step subranging architecture has proven to be a very suitable choice.…”