An 8 bit 0.3–0.8 V 0.2–40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS

Yoshioka, Kentaro; Shikata, Akira; Sekimoto, Ryota; Kuroda, Tadahiro; Ishikuro, Hiroki

doi:10.1109/tvlsi.2014.2304733

Cited by 25 publications

(11 citation statements)

References 13 publications

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“…The reconfigurable ADC [60][61][62][63][64] are in research using pipelined and SAR ADCs to configure the resolution and sampling rate depending upon the requirements. SAR ADC [68][69][70][71][72] is an analog circuit whose performance gets better with CMOS scaling process [73][74][75] and always employed for high speed, low power and high-resolution ADCs. The publication history of SAR ADC is noticeable from last two decades studying its performance enhancement [76][77].…”

Section: Fig 6: Zoomed In View Of Adc Core [21]mentioning

confidence: 99%

Analog to Digital Converters (ADC): A Literature Review

Dalmia

Sinha

2020

E3S Web Conf.

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The signal processing is advancing day by day as its needs and in wireline/wireless communication technology from 2G to 4G cellular communication technology with CMOS scaling process. In this context the high-performance ADCs, analog to digital converters have snatched the attention in the field of digital signal processing. The primary emphasis is on low power approaches to circuits, algorithms and architectures that apply to wireless systems. Different techniques are used for reducing power consumption by using low power supply, reduced threshold voltage, scaling of transistors, etc. In this paper, we have discussed the different types and different techniques used for analog to digital conversion of signals considering several parameters.

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Section: Fig 6: Zoomed In View Of Adc Core [21]mentioning

confidence: 99%

Analog to Digital Converters (ADC): A Literature Review

Dalmia

Sinha

2020

E3S Web Conf.

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“…The proposed approach, shares a similarity with multi-bit per step techniques that have been developed for SAR ADCs [3,[12][13][14][15][16][17][18][19][20][21][22][23][24][25][26] in the aspect of conducting multiple comparisons within one conversion cycle. The difference between this approach and the existing multi-bit per step techniques are the following.…”

Section: Introductionmentioning

confidence: 99%

Exploiting uncertain timing information in time‐based SAR ADCs

Wang

Nagabhushana

Leitner

2020

IET Circuits, Devices & Systems

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Time-based successive approximation register (SAR) analogue-to-digital converters (ADCs) are gaining attraction in ultra-low voltage circuit design. Such ADCs typically use multi-stage voltage controlled delay lines (VCDLs) to perform voltage to time conversion in order to mitigate limited headroom of voltage signals. Although multi-stage VCDLs are used, only the outputs of the final VCDL stages are compared during bit trials. This work demonstrates that additional bit information can be extracted by scavenging timing information revealed at VCDL intermediate stages. The additional bit information can be used to accelerate the ADC conversion process or improve signal-to-noise distortion ratio (SNDR). To cope with uncertainties associated with signals from VCDL intermediate stages, an uncertainty-tolerant SAR procedure is developed. Also, this work presents techniques for adaptively selecting which intermediate stage signals to be tapped along the conversion process. The proposed techniques are applied in the design of a 0.4 V 9-bit SAR ADC in a 130 nm CMOS technology. Silicon measurement results show that with the additional information extracted from VCDL intermediate stages the conversion for the vast majority of ADC inputs can be completed in 7 or 8 clock cycles. Measurement results also demonstrate the potentials of using the intermediate stage signals to improve ADC SNDR.

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“…Recently, there are quite a few low-power or high-performance SAR ADC circuits reported in literature [1][2][3][4][5][6][7][8][9][10]. Typically, SAR ADCs implement the binary search algorithm and require N conversion cycles to generate an N-bit digital output.…”

Section: Introductionmentioning

confidence: 99%

“…Multi-bits per cycle techniques have been used to reduce the total number of conversion cycles [1][2][3][4][5]. This is achieved by simultaneously comparing the ADC input with multiple levels by using multiple comparators.…”

Section: Introductionmentioning

confidence: 99%

“…Nevertheless, the additional hardware required in these designs is still significant. An interesting technique [5] has been presented to reduce the number of comparators; but it negatively affects the circuit speed. To relax the CS array settling requirement, redundancy can be embedded into the search process either by using non-binary search methods [6] or introducing additional compensation steps [7].…”

Section: Introductionmentioning

confidence: 99%

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A novel time and voltage based SAR ADC design with self-learning technique

Nagabhushana

Wang

2016

Proceedings of the 53rd Annual Design Automation Conference

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This paper presents a novel time and voltage based technique for successive approximation register (SAR) analogto-digital converter (ADC) to improve the conversion speed. By taking advantage of the fact that at low supply voltage there will be a significant difference in comparator decision time for different input voltages, the proposed technique creates multiple auxiliary voltage levels for comparison and hence eliminates the need of additional comparators for acceleration as compared with the existing methods. In addition, a digital self-learning module is also presented, which calculates the uncertainty window required for bound update in the proposed method and thus adjusts to different process corners. To validate these concepts, a 10-bit SAR ADC is designed in 130nm CMOS process with 0.5V power supply voltage. The circuit operates in both conventional and proposed modes. Simulations show that the largest number of conversion cycles is 7, hence resulting in an acceleration of 30% over the conventional scheme, while the average number of cycles is 5.58. Simulation results also demonstrate that the proposed method does not affect accuracy. Both ADC operation modes achieve SNDR (signal-tonoise distortion ratio) of 59dB, corresponding to an ENOB (effective number of bits) of 9.5-bits.

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An 8 bit 0.3–0.8 V 0.2–40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS

Cited by 25 publications

References 13 publications

Analog to Digital Converters (ADC): A Literature Review

Analog to Digital Converters (ADC): A Literature Review

Exploiting uncertain timing information in time‐based SAR ADCs

A novel time and voltage based SAR ADC design with self-learning technique

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