An 8.5–11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition

Kocaman, Namik; Fallahi, Siavash; Kargar, Mahyar; Khanpour, M.; Nazemi, Ali; Singh, Ullas; Momtaz, Afshin

doi:10.1109/jssc.2013.2259033

Cited by 44 publications

(16 citation statements)

References 16 publications

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“…Although quadricorrelator frequency detectors (QFDs) can track bidirectionally frequency, the QFD has limited locking range of AE25% in [1,7] and AE13% in [2]. To overcome this problem, bidirectional FDs are presented in [3,8,9].…”

Section: Introductionmentioning

confidence: 99%

A 200 Mb/s∼3.2 Gb/s referenceless clock and data recovery circuit with bidirectional frequency detector

Tho

Son

Kang

2017

IEICE Electron. Express

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This paper presents a 200-Mb/s to 3.2-Gb/s half-rate referenceless clock and data recovery (CDR) circuit in 180 nm CMOS process. A bidirectional frequency detector (FD) is proposed to eliminate the harmonic locking and reduce the frequency acquisition time. A frequency band selector for wide-range the voltage-control oscillator (VCO) is also presented to select an exact frequency band of the VCO. The simulation shows the CDR achieves 11-ps peak-to-peak jitter at 3 Gb/s and the frequency acquisition time of 11.8 µs.

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Section: Introductionmentioning

confidence: 99%

A 200 Mb/s∼3.2 Gb/s referenceless clock and data recovery circuit with bidirectional frequency detector

Tho

Son

Kang

2017

IEICE Electron. Express

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“…The referenceless CDR satisfies this requirement. The referenceless CDR [3][4][5][6][7][8][9][10][11][12][13][14][15][16] extracts the clock signal from the received data signal alone without using any reference clock sources ( Fig. 1(b)).…”

Section: Introductionmentioning

confidence: 99%

“…One solution to this problem is to limit the output frequency of the voltage-controlled oscillator (VCO) in the referenceless CDR to within ± 50 % of the target frequency [3][4][5][6][7]. However, this restriction limits the usable range of input data rate to a narrow range.…”

Section: Introductionmentioning

confidence: 99%

An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors

Kwon¹,

Lim²,

Kim³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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“…Many works, based mainly on the Pottbacker frequency detector (FD) [1], have been reported. In [3] the capture range of the FD is only ±2.4% at 20Gb/s with no capacitor bank in the VCO; in [4] the capture range of the FD is about ±6.4% at 2.75Gb/s, with an 8b resolution of the capacitor bank in the VCO; in [5] the capture range is ±15% at 10Gb/s, with an 11b resolution of the capacitor bank. Thus the Pottbacker FD inherently suffers from a limited capture range, requiring a dedicated FD and a stringent tradeoff between the CDR capture range and the number of VCO bands.…”

mentioning

confidence: 97%

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confidence: 99%

8.8 An 8.2-to-10.3Gb/s full-rate linear reference-less CDR without frequency detector in 0.18μm CMOS

Huang¹,

Cao²,

Green³

2014

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)

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As an alternative to the conventional dual-loop architecture, reference-less CDR architectures have become more popular in industry because of their simplicity and flexibility [1][2][3][4][5]. However, the robustness of the transition between frequency acquisition and phase locking is always a concern, particularly for the linear CDR, which has an extremely limited capture range. Many works, based mainly on the Pottbacker frequency detector (FD) [1], have been reported. In [3] the capture range of the FD is only ±2.4% at 20Gb/s with no capacitor bank in the VCO; in [4] the capture range of the FD is about ±6.4% at 2.75Gb/s, with an 8b resolution of the capacitor bank in the VCO; in [5] the capture range is ±15% at 10Gb/s, with an 11b resolution of the capacitor bank. Thus the Pottbacker FD inherently suffers from a limited capture range, requiring a dedicated FD and a stringent tradeoff between the CDR capture range and the number of VCO bands. In the presence of input jitter and phase-detector (PD) non-idealities, it is difficult to design an architecture where the resolution of the capacitor bank and the turnoff mechanism can guarantee that the VCO frequency will eventually fall within the pull-in range of the CDR. This paper introduces a full-rate reference-less CDR architecture with neither an FD nor a lock detector. Its operation is instead based on the theory that if an offset (or "strobe point") is deliberately introduced into the PD characteristic, the pull-in range will be enhanced as long as the initial frequency offset is the appropriate polarity [6]. For example, if the strobe point (SP) is negative as illustrated in curve (b) of Fig. 8.8.1 and the initial VCO frequency is higher than the input data bit rate, then the VCO frequency will naturally decrease toward the correct frequency since there will be a net discharge of the loop filter during each cycle slip compared with the ideal case as shown in curve (a) of Fig. 8.8.1. Therefore, the linear PD itself can function as an FD with a very high capture range if the polarity of the SP is set appropriately, consistent with the initial VCO frequency.The CDR architecture used to implement this concept is shown in Fig. 8.8.2. Other than those in the digital control circuit (DCC), all signals are differential. The SP of the PD is controlled by voltage V SP , which is generated by the DCC. A frequency-acquisition algorithm is used to set the polarity of the SP and search the correct band in the capacitor bank while in the frequency-acquisition mode (FAM). The resolution of the capacitor bank is only 5 bits, since the "singlesided" pull-in range is sufficiently wide and the requirement for the tuning range in each band does not need to be very stringent.The combined phase detector/strobe point detector (SPD) circuit is shown in Fig. 8.8.3. DFF1, DFF2, BUF1, XOR1, and XOR2 compose a standard Hogge PD. By inserting the two tunable buffers BUF2 and BUF3, the value of the SP can be adjusted overall range of ±15ps by changing the difference between their delays vi...

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An 8.5–11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition

Cited by 44 publications

References 16 publications

A 200 Mb/s∼3.2 Gb/s referenceless clock and data recovery circuit with bidirectional frequency detector

A 200 Mb/s∼3.2 Gb/s referenceless clock and data recovery circuit with bidirectional frequency detector

An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors

8.8 An 8.2-to-10.3Gb/s full-rate linear reference-less CDR without frequency detector in 0.18μm CMOS

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An 8.5–11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition

Cited by 44 publications

References 16 publications

A 200 Mb/s∼3.2 Gb/s referenceless clock and data recovery circuit with bidirectional frequency detector

A 200 Mb/s∼3.2 Gb/s referenceless clock and data recovery circuit with bidirectional frequency detector

An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors

8.8 An 8.2-to-10.3Gb/s full-rate linear reference-less CDR without frequency detector in 0.18&#x03BC;m CMOS

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8.8 An 8.2-to-10.3Gb/s full-rate linear reference-less CDR without frequency detector in 0.18μm CMOS