An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with &amp;gt;10-Hz RF carrier resolution

Rhee, Woogeun; Bisanti, B.; Ali, Akbar

doi:10.1109/4.991389

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2023

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Cited by 23 publications

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Fractional‐N PLL

2023

Phase‐Locked Loops

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Fractional‐N PLL

2023

Phase‐Locked Loops

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Practical Design Aspects in Fractional-N Frequency Synthesis

Rhee¹

2003

Analog Circuit Design

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The demand for low-cost high-performance frequency synthesizers is growing as wireless systems are diversified. High data-rate systems such as general packet radio service (GPRS) need agile frequency switching and require lower in-band phase noise to maintain the same integrated phase error with wider loop bandwidth. Standard frequency synthesizers based on a PLL have difficulties in meeting various specifications due to the fundamental trade-off between loop bandwidth and channel spacing. The circuit noise floor of the synthesizer and spurious tones can be suppressed by narrowing the PLL bandwidth, but the narrowband PLL suffers from long settling time. The narrow loop bandwidth also AbstractThe objective of this work is to present practical design consideration of fractional-N frequency synthesis focusing on different aspects from integer-N frequency synthesizer design. In this work, a fractional-N frequency synthesis technique for high spectral purity is primarily considered. The fractional-N synthesizer offers several advantages over integer-N synthesizers and conventional fractional-N synthesizers. However, superior performance of the fractional-N synthesizer can be possibly limited by noise coupling, nonlinearity, and out-of-band phase noise performance. Design efforts and system perspectives both for the modulator and the PLL are needed to overcome those issues. System and circuit design aspects in fractional-N synthesizer design have been addressed followed by experimental hardware results.

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