An 11-Gb/s Receiver With a Dynamic Linear Equalizer in a 22-nm CMOS

Sumesaglam, T.

doi:10.1109/tcsii.2014.2305217

Cited by 6 publications

(1 citation statement)

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“…This paper proposes the use of active inductors as a load technique to improve the previous circuit. [20]This technique can signi cantly reduce the area of the circuit and can also effectively extend the operating frequency of the circuit.…”

Section: Equalizer Architecture Analysismentioning

confidence: 99%

A 20Gb/s Two-Stage Active Inductor CTLE in 28-nm CMOS

Zhang

Wang

et al. 2022

Preprint

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This paper presents a continuous-time linear equalizer (CTLE) with an active inductor load simultaneously connected in parallel to low frequency branch. The equalizer uses two-stage CTLE, the first stage compensating for high-frequency (HF) attenuation and the second stage equalizer compensates medium-frequency (MF) and HF by parallel low-frequency branches. The MF stage is used for the long-tail Intern symbol interference (ISI) equalization to minimize residual ISI. Equalizer with voltage control capacitor to configure the distribution of zero poles, for the HF has a configurable range of 0.5dB.The low-frequency gain can be configured by changing the load current of the active inductor to reduce the effect of parasitic resistance on the layout. The layout size is 5.9um*6um based on a 28nm CMOS process. The post layout results show that the equalizer has a maximum compensation capability of 10.37dB at a rate of 20Gb/s with an eye width of 0.85UI.

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Section: Equalizer Architecture Analysismentioning

confidence: 99%