An 11-bit 160-MS/s Non-binary C-based SAR ADC with a Partially Monotonic Switching Scheme

Lee, Jae-Hyuk; Lee, Seung‐Hoon; Boo, Jun-Ho; Park, Jun-Sang; An, Tai-Ji; Shin, Hee-Wook; Cho, Young-Jae; Choi, Michael; Burm, Jinwook; Ahn, Gil-Cho

doi:10.5573/jsts.2023.23.2.118

Cited by 1 publication

(2 citation statements)

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“…In order to obtain high-quality biometric signals (digital signals), low-noise amplifiers and medium-high precision ADCs are required [3]. In recent years, SAR ADCs have gained popularity as low-power ADCs [4-6 lations have shown that the DAC capacitor array usually accounts for a large pa overall power consumption of SAR ADCs [7,8]. In order to cope with this energy st a number of energy-saving schemes have recently been proposed, including ER Tri-level [10], VMS [11] and Hybrid [12].…”

Section: Introductionmentioning

confidence: 99%

“…That of the C-2C common-mode voltag In recent years, SAR ADCs have gained popularity as low-power ADCs [4][5][6]. Simulations have shown that the DAC capacitor array usually accounts for a large part of the overall power consumption of SAR ADCs [7,8]. In order to cope with this energy structure, a number of energy-saving schemes have recently been proposed, including ERMS [9], Tri-level [10], VMS [11] and Hybrid [12].…”

Section: Introductionmentioning

confidence: 99%

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A Hybrid Energy-Efficient, Area-Efficient, Low-Complexity Switching Scheme in SAR ADC for Biosensor Applications

Hu,

Chen,

Huang

et al. 2023

Micromachines

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A hybrid energy-efficient, area-efficient, low-complexity switching scheme in SAR ADC for biosensor applications is proposed. This scheme is a combination of the monotonic technique, the MSB capacitor-splitting technique, and a new switching method. The MSB capacitor-splitting technique, as well as the reference voltage Vaq allow for more options for reference voltage conversion, resulting in higher area savings and higher energy efficiency. In a capacitor array, the circuit performs unilateral switching during all comparisons except for the second and last two comparisons, reducing the difficulty in designing the drive circuit. The proposed switching scheme saves 98.4% of the switching energy and reduces the number of unit capacitors by 87.5% compared to a conventional scheme. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low-sampling error-sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrated that the proposed SAR ADC achieves 61.51 dB SNDR, 79.21 dB SFDR and consumes 0.278 μW of power in a 180 nm process with a 1 V power supply, a full swing input signal frequency of 23.33 kHz, and a sampling rate of 100 kS/s.

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