1999
DOI: 10.1109/16.760390
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An 0.1-μm voidless double-deck-shaped (DDS) gate HJFET with reduced gate-fringing-capacitance

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Cited by 6 publications
(1 citation statement)
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“…In essence, this is a triple-recess process that results in an InAlAs barrier layer thickness t ins of about 4 nm. The T-shaped gate with a Ti/Pt/Au (20/20/350 nm) metal stack is fabricated through a SiO 2 -assisted process with a stem height of 150 nm to minimize parasitic capacitance [3], [8]. The device has a T-type gate layout.…”
Section: Process Technologymentioning
confidence: 99%
“…In essence, this is a triple-recess process that results in an InAlAs barrier layer thickness t ins of about 4 nm. The T-shaped gate with a Ti/Pt/Au (20/20/350 nm) metal stack is fabricated through a SiO 2 -assisted process with a stem height of 150 nm to minimize parasitic capacitance [3], [8]. The device has a T-type gate layout.…”
Section: Process Technologymentioning
confidence: 99%