AMD 3DNow! technology: architecture and implementations

Oberman, Stuart F.; Favor, Greg; Weber, Franz

doi:10.1109/40.755466

Cited by 101 publications

(54 citation statements)

References 4 publications

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“…One direction adds basic operations for 3D graphics into general purpose processor ISAs as extensions, such as SSE-2 extension to Intel x86 [5], AltiVec extension to PowerPC [6], 3DNow! in AMD x86 [7], and MIPS-3D extension to MIPS64 [8]. However, these processors are more targeted for traditional workloads such as business and scientific applications.…”

Section: Past Workmentioning

confidence: 99%

Adding 3D graphics support to PLX

Yang

Lee

2003

International Conference on Information Technology: Research and Education, 2003. Proceedings. ITRE2003.

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Abstract-PLX is a compact, fully subword-parallel instruction set architecture (ISA) for very fast multimedia processing. This paper adds floating-point instructions to PLX for 3D graphics processing, which is essential for applications such as games and digital content creation. Based on an analysis of the 3D graphics pipeline from an ISA point of view, we show the operations and data types needed. We present the FP ISA and demonstrate its use and performance with code examples from the 3D graphics pipeline.

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Section: Past Workmentioning

confidence: 99%

Adding 3D graphics support to PLX

Yang

Lee

2003

International Conference on Information Technology: Research and Education, 2003. Proceedings. ITRE2003.

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“…These applications include scientific computing, computer graphics, 3D graphics applications and computer aided design (CAD) [1][2][3][4]. Although software routines can approximate elementary functions accurately, they are often too slow for numerically intensive and real-time applications.…”

Section: Introductionmentioning

confidence: 99%

Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations

2016

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This paper presents a method for designing linear, quadratic and cubic interpolators that compute elementary functions using truncated multipliers, squarers and cubers. Initial coefficient values are obtained using a Chebyshev series approximation. A direct search algorithm is then used to optimize the quantized coefficient values to meet a user-specified error constraint. The algorithm minimizes coefficient lengths to reduce lookup table requirements, maximizes the number of truncated columns to reduce the area, delay and power of the arithmetic units, and minimizes the maximum absolute error of the interpolator output. The method can be used to design interpolators to approximate any function to a user-specified accuracy, up to and beyond 53-bits of precision (e.g., IEEE double precision significand). Linear, quadratic and cubic interpolator designs that approximate reciprocal, square root, reciprocal square root and sine are presented and analyzed. Area, delay and power estimates are given for 16, 24 and 32-bit interpolators that compute the reciprocal function, targeting a 65 nm CMOS technology from IBM. Results indicate the proposed method uses smaller arithmetic units and has reduced lookup table sizes compared to previously proposed methods. The method can be used to optimize coefficients in other systems while accounting for coefficient quantization as well as truncation and rounding effects of multiple arithmetic units.

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“…BroadcastBit,4,0 R1, R2 0x0F0F0F0F BroadcastBit,4,1 R1, R2 0x00FF00FF BroadcastBit,8,0 R1, R2 0xFFFFFFFF The BroadcastBit instruction can be added to an ISA with little overhead because it requires only small control modifications to the functional unit that does parallel addition with saturation, which is included in almost all subword instruction sets [1][2][3][4][5]17]. When saturation occurs during an addition, all bits in a subword are set to 0s or 1s.…”

Section: Results In R2mentioning

confidence: 99%

“…Logical operations AND, OR, and NOT along with SHIFT are common bit-level operations. Today, most processor ISAs support subword parallel computation [1][2][3][4][5][6]. Subwords are data items that are smaller than a word.…”

Section: Introductionmentioning

confidence: 99%