Ambipolar SB-FinFETs: A New Path to Ultra-Compact Sub-10 nm Logic Circuits

Canan, Talha Furkan; Kaya, Savaş; Kodi, Avinash; Xin, Hao; Louri, Ahmed

doi:10.1109/ted.2018.2874000

Cited by 7 publications

(6 citation statements)

References 21 publications

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“…However, with transistors’ channel lengths approaching nanometer sizes, traditional bulk Si field-effect transistors (FETs) will face with enormous challenges because of the emerging short-channel effects . To enable continued FETs scaling, FETs with a novel device structure (e.g., Si nanowires (NWs), − ultrathin Si on insulator (UTSOI), , and Si Fin configurations − ) or adopted alternative channel materials (e.g., carbon nanotubes (CNT)) may provide a viable alternative to sustain the Moore’s law in the next decade.…”

Section: Introductionmentioning

confidence: 99%

Performance of Monolayer Blue Phosphorene Double-Gate MOSFETs from the First Principles

Wang

Cai

Lei

et al. 2019

ACS Appl. Mater. Interfaces

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We systematically study the device characteristics of the monolayer (ML) blue phosphorene metal–oxide semiconductor field-effect transistors (MOSFETs) by using ab initio quantum-transport simulations. The ML blue phosphorene MOSFETs show superior performances with ultrashort-channel length. We first predict the ultrascaled ML blue phosphorene MOSFETs with proper doping concentration and underlap structures are compliant with the high-performance (HP) and low-power (LP) requirements of the International Technology Roadmap for Semiconductors in the next decade in the aspects of the on-state current, delay time, and power dissipation. Encouragingly, the performances of the ML blue phosphorene MOSFETs are superior to that of the MOSFETs based on arsenene, antimonene, InSe, etc. in terms of the on-state current at similar device size. We also consider the electron–phonon scattering in 10.2 nm gate ML blue phosphorene MOSFET. It is found that the on-state current with the scattering of the blue phosphorene device is degraded by 25.4 and 23.6% for HP and LP applications, which can also fulfill the HP and LP application target. Therefore, we can deduce that ML blue phosphorene is an alternative channel material to silicon for ultrascaled FETs if the large-scale and high-quality blue phosphorene can be achieved.

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Section: Introductionmentioning

confidence: 99%

Performance of Monolayer Blue Phosphorene Double-Gate MOSFETs from the First Principles

Wang

Cai

Lei

et al. 2019

ACS Appl. Mater. Interfaces

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“…Similarly, in the opposite arrangement, a NOR logic operation is also confirmed. Moreover, in all cases, the logic gates are found to operate correctly with supply voltages as low as 0.6 V and gate lengths as short as 5 nm using this exact same arrangement of WFs [4]. Thus, together with the use of 2T-XOR gates, WFE can be used to design ultracompact logic circuits in terms of transistor count and area required.…”

Section: B Nand and Normentioning

confidence: 80%

“…[20], [21]. Thus, it is clear that the ability to set independent gate WFs in a single FinFET enables designers to pursue novel circuits as explored next [4].…”

Section: Device Structures and Modelingmentioning

confidence: 99%

“…This is accomplished by setting the S/D contacts at the same WF (5.0 eV) and specific adjustments to the independent (top and bottom) gates as necessary to configure each gate for a given logic function. This must be done with care so that not only devices work with acceptable static and dynamic performance but also utilize as few metals as possible, to avoid process complexity and cost [4].…”

Section: Ultracompact Logic Gatesmentioning

confidence: 99%

“…Although less revolutionary, this ''more-of-Moore'' approach can provide additional time for the paradigm-shifting alternatives to Si CMOS to be developed fully [3]. Recently, we proposed such an effort via gate workfunction engineering (WFE) that can extend FinFET-based logic design down to 5 nm while also resulting in ultracompact XOR/NAND/NOR logic gates with significant reduction in area (∼50%) and power dissipation (up to ×10) [4]. In the proposed gates, the WFE is selectively applied to Schottky-barrier (SB) FinFETs with independent gate inputs, which leads to entirely novel logic elements such as single transistor (1T) CMOS pass-gates as well as 3T/4T XOR gates and 2T NAND/NOR gates with noninverting inputs.…”

Section: Introductionmentioning

confidence: 99%

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Ultracompact and Low-Power Logic Circuits via Workfunction Engineering

Canan

Kaya

Kodi

et al. 2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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An extensive analysis of sub-10-nm logic building blocks utilizing ultracompact logic gates based on recently proposed gate workfunction engineering (WFE) approach is provided. WFE sets the WF in the contacts as well as two independent gates of an ambipolar Schottky-barrier (SB) FinFET to alter the threshold of two channels, as a unique leverage to modify the logic functionality out of a single transistor. Thus, a single transistor (1T) CMOS pass-gate, 2T NAND and NOR gates as well as 3T or 4T XOR gates with substantial reduction in overall area (50%) and power (up to ×10) dissipation can be implemented. To harness this potential and illustrate the capabilities of these compact ambipolar transistors, novel logic building blocks, including 6T multiplexer, 8T full-adder, 4T latch, 6T D-type flip-flop, and 4T AND-OR-invert (AOI) gates, are developed. Besides the logic verification using 7-nm devices, the dynamic performance of the proposed logic circuits is also analyzed. The comparative simulation study shows that WFE in independent-gate SB-FinFETs can lead to absolutely minimalist CMOS logic blocks without significant degradation to overall power-delay product (PDP) performance. INDEX TERMS 3T-XOR, 4T AND-OR-invert (AOI), 6T 4-to-1 multiplexer (MUX), ambipolar, CMOS logic gates, nanotechnology, Schottky-barrier MOSFET, tunneling.

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