Alternative software architectures for parallel protocol execution with synchronous IPC

Woodside, C. Murray; Franks, R.G.

doi:10.1109/90.222925

Cited by 5 publications

(5 citation statements)

References 22 publications

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“…Hardware implementations for high speed protocols have been proposed in [13]. Special attention has been paid to the parallelization of protocol implementations, so for example in [5] and [24]. However, the parallelization proposed in these papers depends entirely on the intuition of the designer and thus its efficiency may be non-optimal.…”

Section: Introductionmentioning

confidence: 99%

From SDL Specifications to Optimized Parallel Protocol Implementations

Leue

Oechslin

1995

IFIP Advances in Information and Communication Technology

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We propose a formalized method that allows to automatically derive an optimized implementation from the formal specification of a protocol. Our method starts with the SDL specification of a protocol stack. We first derive a data and control flow dependence graph from each SDL process. Then, in order to perform cross-layer optimizations we combine the dependence graphs of different SDL processes. Next, we determine the common path through the multi-layer dependence graph. We then parallelize this graph wherever possible which yields a relaxed dependence graph. Based on this relaxed dependence graph we interpret different optimization concepts that have been suggested in the literature, in particular lazy messages and combination of data manipulation operations. Together with these interpretations the relaxed dependence graph can be be used as a foundation for a compile-time schedule on a sequential or parallel machine architecture. The formalization we provide allows our method to be embedded in a more comprehensive protocol engineering methodology.

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Section: Introductionmentioning

confidence: 99%

From SDL Specifications to Optimized Parallel Protocol Implementations

Leue

Oechslin

1995

IFIP Advances in Information and Communication Technology

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“…[5] measures the impact of several implementations of the transport and session layers in the OSI reference model using an ADA-like rendezvous-style of Layer Parallelism in a nonuniform access shared memory environment. [9] measures the performance of a Functional Parallelism process architecture for presentation layer and transport layer functionality on a shared memory multi-processor.…”

Section: Related Workmentioning

confidence: 99%

“…However, these two types of process architectures exhibit significantly different performance characteristics that are affected by the underlying operating system and hardware platform. For instance, on shared memory multi-processor platforms, taskbased process architectures often result in high data movement and context switching overhead [5]. Likewise, in a message-passing transputer multi-processor environment, message-based process architectures typically result in high levels of synchronization overhead [2].…”

Section: Introductionmentioning

confidence: 99%

Measuring the Impact of Alternative Parallel Process Architectures on Communication Subsystem Performance

Schmidt

Suda

1995

IFIP Advances in Information and Communication Technology

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“…The value of ¾ for a 4WS is calculated from figure 6 since at least two simultaneous senders were required to offer an adequate load. 8 The snd plot and the rcv (4WS) plot overlap in almost all points.…”

Section: Figure 4 Performance Of Parallel Packet Screen Based On Fasmentioning

confidence: 94%

“…There are many methods of distributing the load among a number of processors 3 [8]. Two basic approaches can be taken, in order to speed up processing.…”

Section: Packet Parallelismmentioning

confidence: 99%

A parallel packet screen for high speed networks

Benecke¹

Proceedings 15th Annual Computer Security Applications Conference (ACSAC'99)

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This paper demonstrates why security issues related to the continually increasing bandwidth of High Speed Networks (HSN) cannot be addressed with conventional firewall mechanisms. A single packet screen running on a fast computer is not capable of filtering all packets traversing a Fast/Gigabit Ethernet. This problem can be addressed by using parallel processing methods to implement a fast, scalable packet screen for Ethernets. The paper shows how hardware may be utilized to distribute the network load among such parallel packet screens. Empirical results using 'off-the-shelf' equipment indicate that this approach is usable.

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Alternative software architectures for parallel protocol execution with synchronous IPC

Cited by 5 publications

References 22 publications

From SDL Specifications to Optimized Parallel Protocol Implementations

From SDL Specifications to Optimized Parallel Protocol Implementations

Measuring the Impact of Alternative Parallel Process Architectures on Communication Subsystem Performance

A parallel packet screen for high speed networks

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