Alpha-particle induced charge transfer between closely spaced trench capacitor memory cells

Abstract

A detailed analysis of various mechanisms involved in alpha-particle induced charge transfer between two trench type dRAM cells is reported and an analytical model has been developed to represent the transfered charge. The results compare very favorably with detailed simulation results.UANTITATIVE modeling of the upsets due to alphaarticles has become necessary for development of e large dRAM's. Furthermore, due to purely geometrical factors, the probability of an alpha-particle track intersecting two adjacent cells in trench type storage devices becomes significant as separations shrink. It is then essential to understand how the charge transfer under these conditions differs from that occurring in the much studied single cell case. Convincing qualitative arguments have been offered which assert that the alpha-particle track will act as a plasma wire which short circuits the two cells. Under this model the two cells will ultimately be brought to the same potential unless the cell capacitance is so large that the plasma track dissipates by radial spreading before the charge transfer is complete.We have developed analytical models which describe this situation. These models were stringently tested by applying them to two-dimensional (2-D) structures under a wide variety of conditions and comparing the results to those obtained from our modified version of the 2-D device simulator, PISCES. Predictions from the analytic model compared very favorably with the results of numerical simulation. It is shown below that the analytical models are directly applicable to the threedimensional (3-D) case.This letter presents numerical values for the charge transfer in 3-D structures and provides a brief description of the physics of this phenomenon with emphasis on the ways it differs from the single cell problem.As a result of 2-D simulations on structures such as that shown in Fig. 1, it has been found that an alpha particle track intersecting two trenches can look like a "plasma wire" shorting the trenches. (See Fig. 2 t = 0.3 ps curve.) However the wire starts to "dissolve" in a few picoseconds (Fig. 2 t = 20 ps) greatly reducing its potential as a powerful charge transfer mechanism. The duration of alpha-particle induced shorting is much less than expected on the basis of conventional analysis since it is governed by mechanisms other than the conventionally assumed radial ambipolar diffusion rate.

System effects of single event upsets

“…However, an SEU is not necessarily a single upset; for instance, multiple bit faults occur due to single ionizing particles [5,32]. Another failure mode in highdensity memories which leads to multiple bit faults is alpha particle induced charge transfer between cells [10]. The present model might be extended to analyze this, provided that realistic multiple digit fault rates could be established.…”

“…That is, ECCs for digits are developed by working over the Galois field GF(2 w ), where a digit is w bits. For example, there is a (17,15,3) code over GF (2 4 ) which can be shortened to a (10,8,3) code. The (10,8,3) code encodes 8 digits, of 4 bits each, into 10 digits, of 4 bits each.…”

“…a Single Event Upset (SEU), in computer memory or combinational logic circuits. SEU effects are found at sea level [24,31], in airborne avionics [19,20], and in space [1,2,5,7,10,12,14,23,24,25,26,27,28,32]. The effect of SEUs on chips has been extensively investigated and programs, e.g.…”

Prevention of Single Event Upsets in Microelectronics

“…Circuits vulnerable to upset resulting from "ion shunt" charge transport [95], including devices with multilayer structures [96,97) and those with closely spaced deep nodes [98], upset due to charge transported through the singleevent track, rather than due to charge collected from the ion track. In these cases, critical charge, being a circuit characteristic remains a valid vulnerability measure, but collected charge and critical LET do not have the same relationships to device vulnerability as they do in other technologies.…”

“…Ia addition, a single ion track can deposit charge onto multiple DRAM cells, resulting in multiple-bit upset from a single event [101][102][103][104][105]. TCDRAMs are also vulnerable to upset from ion shunts [98]. Anticipated directions for the evolution of TCDRAM technology include the use of high dielectric-constant and/or ferroelectric materials for the charge-storage capacitors, and the incorporation of isolation tec nologies to place each cell or some small group of cell in dielectrically isolated regions.…”