All-synthesizable 6Gbps voltage-mode transmitter for serial link

Choi, Young‐Ho; Seong, Kihwan; Kim, Byungsub; Sim, Jae‐Yoon; Park, Hong-June

doi:10.1109/asscc.2016.7844181

Cited by 2 publications

(2 citation statements)

References 5 publications

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“…High-speed serializer/de-serializer (SerDes) technology is extensively employed to improve the data transmission performance of wireline transmission systems [1]. Due to the continuous development of data-intensive services, such as the Internet of Things, cloud computing, and cloud storage, telecommunication infrastructure is required to be upgraded; therefore, the requirements for the data transmission rate of SerDes should be increased [2][3][4][5].…”

Section: Introductionmentioning

confidence: 99%

An 8-Gbps, Low-Jitter, Four-Channel Transmitter with a Fractional-Spaced Feed-Forward Equalizer

et al. 2022

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An 8 gigabits per second (Gbps), low-jitter, four-channel transmitter with fractional-spaced feed-forward equalizer (FFE) is designed to meet the demand for broad transmission bandwidth in serial data communications. A novel frequency divider chain (FDC) architecture is developed, to satisfy the time requirements for high-speed data serialization. Moreover, a reconfigurable output driver circuit is employed to ensure compatibility with different protocols. In addition, a three-tap fractional-spaced FFE, which can enhance signal bandwidth significantly, is proposed, to compensate for channel loss. The transmitter was simulated and validated based on the Semiconductor Manufacturing International Corporation (SMIC) 55-nm process. The post-layout simulation results show the following: The tuning range of the phase-locked loop (PLL) can cover 1.6 to 4.6 GHz. At an output frequency of 4 GHz, the root-mean-square jitter (RJ) of the PLL after integration from phase noise was 1.93 ps. With an 8 Gbps output data rate, using the pseudo-random binary sequence (PRBS)-31 as a data source to simulate the whole transmitter, the power consumption values of the PLL and drive circuit were 27.0 and 29.2 mW, respectively, and the eye width and the valid eye height of output data were 0.76 unit interval (UI) and 0.68.

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Section: Introductionmentioning

confidence: 99%

An 8-Gbps, Low-Jitter, Four-Channel Transmitter with a Fractional-Spaced Feed-Forward Equalizer

et al. 2022

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“…On the other hands, the performance of analog ICs designed with advanced CMOS process are limited by low intrinsic device gains, large leakage current and low supply voltage. Therefore, digital implementations of analog and mixed signal ICs become more and more attractive [1][2][3][4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits

Yang

Zhao

et al. 2019

Sci. China Inf. Sci.

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This paper proposes a synthesized injection-locked bang-bang phased-locked loop (SILBBPLL) with high digital controlled oscillator (DCO) frequency resolution. The SILBBPLL is expressed with hardware description language and automatically placed & routed (APR) by using standard digital circuit design flow. As the mismatch issues of the circuits are not considered carefully during the APR design flow, the phase noise performance is severely deteriorated. We adopt pulse injection locking technique to improve the phase noise performance. The DCO frequency resolution is critical for reducing the reference spur in a digital injection-locked PLL. Therefore, we propose novel frequency tuning circuits to increase the DCO frequency resolution so that the reference spurs are reduced. The frequency tuning circuits consist of a standard cell based high-linearity output feedback DAC (OFDAC) and two custom varactors. The OFDAC is used to tune the frequency of the DCO with the custom varactor precisely. The custom varactor is firstly designed, added into the standard cell library, and APR with the standard cells. The SILBBPLL chip with a core area of 0.008 mm 2 is implemented in 65 nm CMOS process. When operating at 1.8 GHz, the measured results show that the root-mean-square (RMS) jitter integrated from 10 kHz to 100 MHz is 1.1 ps, and the power consumption is 1.5 mW with a 0.8-V supply. The proposed SILBBPLL achieves a figure-of-merit (FoM) of −237.4 dB and a reference spur of −50.9 dBc. Keywords synthesized all-digital phased-locked loops (ADPLL), bang-bang phased-locked loop (BBPLL), automatically placed & routed (APR), output feedback DAC (OFDAC), injection-locked Citation Yang J C, Zhang Z, Qi N, et al. A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits.

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All-synthesizable 6Gbps voltage-mode transmitter for serial link

Cited by 2 publications

References 5 publications

An 8-Gbps, Low-Jitter, Four-Channel Transmitter with a Fractional-Spaced Feed-Forward Equalizer

An 8-Gbps, Low-Jitter, Four-Channel Transmitter with a Fractional-Spaced Feed-Forward Equalizer

A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits

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