All Digital Low-Overhead SAR ADC Built-In Self-Test for Fault Detection and Diagnosis

Ganji, Mona; Saikiran, Marampally; Chen, Degang

doi:10.1109/vts52500.2021.9794271

Cited by 10 publications

(6 citation statements)

References 9 publications

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“…23 shows our implementation of the CDAC switches. All the circuits in our ADC are same as presented in [24].…”

Section: Circuit Under Test: Sar Adcmentioning

confidence: 99%

“…The testing scheme implemented to test the three segmented 18-bit SAR ADC CDAC is the one hot encoding strategy [24]. It is based on the analysis of the charge conservation in the capacitive DAC.…”

Section: One Hot Encodingmentioning

confidence: 99%

“…Careful analysis in [24] showed that, by performing a one hot test for bit k we can detect faults in bit k to the MSB. However, the offset of the comparator, process variations, and mismatches limit this detection.…”

Section: One Hot Encodingmentioning

confidence: 99%

“…In this section, we are going to discuss how we validated our time efficient defect testing simulation framework on a data converter circuit. For this exercise, we implemented a BIST presented in [24] that performs a structural test for an 18-bit SAR ADC's Capacitive DAC based on the natural operation of the ADC.…”

mentioning

confidence: 99%

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Low-Cost Defect Simulation Framework for Analog and Mixed Signal (AMS) Circuits with Enhanced Time-Efficiency

Saikiran

Sekyere

Ganji

et al. 2022

Preprint

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Defect-oriented testing is becoming increasingly popular in recent times, especially in safety-critical applications in automotive, space and medical industries. The stringent quality requirements from these industries such as zero defective parts per million (DPPM) necessities a need to have efficient defect testing methods. Furthermore, the overall development time of integrated circuit can be reduced by reducing the defect simulation time. In this work, we present a simple and time-efficient defect simulation framework for pre-silicon testing of AMS circuits. In our method, a given defect model is realized using Verilog-A modules and tests multiple defects in a circuit in a single-run simulation. In contrast to the conventional defect simulation framework, our method saves simulation time by avoiding the repetitive work of generating a netlist for each defect and by reducing the time overhead for the simulator to interface with data/file-handling system. To strongly validate our proposed framework, we use diverse AMS circuits such as operational amplifier (op amp), fast transient flipped-voltage follower based low-dropout regulator (FVF LDO) and Successive-approximation-register (SAR) analog-to-digital converters (ADC). For DC testing schemes used for op amp and LDO testing, we show that our proposed framework reduces the simulation time to less than one-tenth (1/10th) in comparison with conventional framework. On the other hand, for the transient testing scheme, the proposed framework reduces the simulation time to less than 50% of the conventional framework. Furthermore, we also show that there is no negative impact on the defect coverage using the proposed framework.

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“…23 shows our implementation of the CDAC switches. All the circuits in our ADC are same as presented in [24].…”

Section: Circuit Under Test: Sar Adcmentioning

confidence: 99%

Section: One Hot Encodingmentioning

confidence: 99%

Section: One Hot Encodingmentioning

confidence: 99%

mentioning

confidence: 99%

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Low-Cost Defect Simulation Framework for Analog and Mixed Signal (AMS) Circuits with Enhanced Time-Efficiency

Saikiran

Sekyere

Ganji

et al. 2022

Preprint

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show abstract

“…Others also utilizes the multi-site testing capabilities of modern automated test equipment (ATE) to reduce test time [3,[13][14]. More recently, several design for test and build in self-test methods [15][16][17][18] have all been proposed as strategies to ensure continued reliability of IC through online health monitoring. Several high coverage op amp defect detection methods [19][20][21][22][23][24][25][26] have all been proposed.…”

Section: Introductionmentioning

confidence: 99%

Defect Detection and Localization in Operational Amplifiers using Digital Control and Monitor Circuits

Sekyere,

Marampally,

Chen

2023

Preprint

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Operational amplifiers (op amps) are fundamental blocks that find wide application both as stand-alone devices and as crucial building blocks embedded in various Systems on Chips (SoCs). Achieving high defect coverage as well as performing diagnosis and defect localization in these circuits has been proven to be a difficult/expensive task even with sophisticated analog and digital testing circuitry. ISO26262 Standard for functional safety (FuSa) places stringent requirement that an automotive IC must have a very high defect coverage (usually greater than 90%). This reinforce the need to improve the robustness in the design of analog and mixed signal (AMS) circuits to ensure their reliability especially if they are used in mission critical industries. This paper presents a simple defect detection, diagnosis, and localization method for op amps including Widlar current reference and biasing circuitry and can be used both for production and in-field tests for online health monitoring to ensure continued reliability during integrated circuits’ (IC) lifetime. We rigorously validate all our results using extensive transistor-level simulations of two op amps architectures (folded cascode and telescopic) designed in MUSE TSMC 180nm technology. For the folded cascode op amp, the proposed method achieves a worst-case defect coverage of 94.5% and a best-case coverage of 98%. Similarly for the telescopic op amp, the proposed method attains a worst- and best-case defect coverage of 97% and 99% respectively. Furthermore, in this work, we also propose a defect diagnosis and localization strategy using recorded bit streams from states of digital injectors and detectors.

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Low-cost defect simulation framework for analog and mixed signal (AMS) circuits with enhanced time-efficiency

Saikiran

Sekyere

Ganji

et al. 2023

Analog Integr Circ Sig Process

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All Digital Low-Overhead SAR ADC Built-In Self-Test for Fault Detection and Diagnosis

Cited by 10 publications

References 9 publications

Low-Cost Defect Simulation Framework for Analog and Mixed Signal (AMS) Circuits with Enhanced Time-Efficiency

Low-Cost Defect Simulation Framework for Analog and Mixed Signal (AMS) Circuits with Enhanced Time-Efficiency

Defect Detection and Localization in Operational Amplifiers using Digital Control and Monitor Circuits

Low-cost defect simulation framework for analog and mixed signal (AMS) circuits with enhanced time-efficiency

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