Aligned silicon nanofins via the directed self-assembly of PS-b-P4VP block copolymer and metal oxide enhanced pattern transfer

Abstract

'Directing' block copolymer (BCP) patterns is a possible option for future semiconductor device patterning, but pattern transfer of BCP masks is somewhat hindered by the inherently low etch contrast between blocks. Here, we demonstrate a 'fab' friendly methodology for forming well-registered and aligned silicon (Si) nanofins following pattern transfer of robust metal oxide nanowire masks through the directed self-assembly (DSA) of BCPs. A cylindrical forming poly(styrene)-block-poly(4-vinyl-pyridine) (PS-b-P4VP) BCP was employed producing 'fingerprint' line patterns over macroscopic areas following solvent vapor annealing treatment. The directed assembly of PS-b-P4VP line patterns was enabled by electron-beam lithographically defined hydrogen silsequioxane (HSQ) gratings. We developed metal oxide nanowire features using PS-b-P4VP structures which facilitated high quality pattern transfer to the underlying Si substrate. This work highlights the precision at which long range ordered ∼10 nm Si nanofin features with 32 nm pitch can be defined using a cylindrical BCP system for nanolithography application. The results show promise for future nanocircuitry fabrication to access sub-16 nm critical dimensions using cylindrical systems as surface interfaces are easier to tailor than lamellar systems. Additionally, the work helps to demonstrate the extension of these methods to a 'high χ' BCP beyond the size limitations of the more well-studied PS-b-poly(methyl methylacrylate) (PS-b-PMMA) system.

Strategies for Inorganic Incorporation using Neat Block Copolymer Thin Films for Etch Mask Function and Nanotechnological Application

“…[ 129 ] Of late, hemispherical Fe 3 O 4 nanodots were utilized as catalysts for germanium nanowire growth that possessed coherent twin boundaries perpendicular to the nanowire growth direction. [ 157 ] Thus far, Fe 3 O 4 , [ 129,138,139 ] CeO 2 , [ 128,131 ] CuO, [ 128 ] and Al 2 O 3 [ 139,140 ] patterning of nanodot and nanowire features have been developed using the metal salt inclusion methodology and have been shown to be effective on-chip etch masks on silicon (see examples in Figure 13 and Table 2 ). Fe 3 O 4 inclusion has been shown to be effective in a low molecular weight lamellar PS-b -P4VP system for line space features with a pitch of ≈10 nm.…”

“…a,b) Reproduced with permission. [ 139 ] Copyright 2015, Royal Society of Chemistry. 1-3) Reproduced with permission.…”

“…We have also integrated the metal-salt inclusion technique in graphoepitaxy schemes with similar effi cacy in PS-b -P4VP for patterning aligned Si and Ge nanofi ns as shown in Figure 14 . [139][140][141] "Activated" PS-b -P4VP line pattern and metal salt inclusion producing Fe 3 O 4 , Al 2 O 3 and HfO 2 nanowires have been employed as robust on-chip etch masks with similar effi cacy for pattern transfer. These achievements are pertinent for DSA technology as pattern transfer fi delity is critical.…”

“…[ 158 ] Silicon nanopillars of 500 nm in height can be obtained following ICP etching of metal oxide nanodot patterns. [ 127,129,138 ] Additionally, nanowires were developed in the same way for both BCP systems, PS-b -PEO and PS-b -P4VP, resulting in highly uniform Fe 3 O 4 nanowires with 42 nm (PS-b -PEO) [ 134 ] and 32 nm (PS-b -P4VP) [ 139 ] periodicity. We have also integrated the metal-salt inclusion technique in graphoepitaxy schemes with similar effi cacy in PS-b -P4VP for patterning aligned Si and Ge nanofi ns as shown in Figure 14 .…”

Parallel Arrays of Sub-10 nm Aligned Germanium Nanofins from an In Situ Metal Oxide Hardmask using Directed Self-Assembly of Block Copolymers

“…[17][18][19] Likewise, metal oxide inclusion has been reported to significantly enhance 2 "activated" PS-b-PEO and PS-b-P4VP BCP systems for Si nanofeature fabrication. [20][21][22][23] In order to extend the relentless dimensional scaling of semiconductor features (i.e. Moore's Law) to the deep nanoscale regime (< 10 nm), employing DSA of BCP nanopatterns has emerged as a cost-effective route to controllably fabricate device-relevant features on a wafer scale level.…”