ALIGN: A System for Automating Analog Layout

Dhar, Tonmoy; Kunal, Kishor; Li, Yaguang; Madhusudan, Meghna; Poojary, Jitesh; Sharma, Arvind Kumar; Xu, Wenbin; Burns, Steven; Harjani, Ramesh; Hu, Jiang; Kirkpatrick, Desmond A.; Mukherjee, Parijat; Yaldiz, Soner; Sapatnekar, Sachin S.

doi:10.1109/mdat.2020.3042177

Cited by 36 publications

(9 citation statements)

References 15 publications

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“…These concepts have been discussed in several works [127] [136], where the routing constraints have to be successfully propagated through the system hierarchy, and, the different pins/ports made available to the levels below/above. Similarly, in ALIGN (2019-2021) [169]- [172], electrical performance metrics for the system are percolated down to individual sub-blocks and translated into layout rules, with the specific routing tasks being integrated into each hierarchical level.…”

Section: Hierarchical Routingmentioning

confidence: 99%

Analog Integrated Circuit Routing Techniques: An Extensive Review

Martins

Lourenço

2023

IEEE Access

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Section: Hierarchical Routingmentioning

confidence: 99%

Analog Integrated Circuit Routing Techniques: An Extensive Review

Martins

Lourenço

2023

IEEE Access

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“…As a result, automated design of analog circuits is not as mature as its digital counterpart. Nevertheless, ML has been employed also for analog design [62], [63].…”

Section: Analog Physical Designmentioning

confidence: 99%

MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper

Rapp

Amrouch

Lin

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Due to the increasing size of integrated circuits (ICs), their design and optimization phases (i.e., computer-aided design, CAD) grow increasingly complex. At design time, a large design space needs to be explored to find an implementation that fulfills all specifications and then optimizes metrics like energy, area, delay, reliability, etc. At run time, a large configuration space needs to be searched to find the best set of parameters (e.g., voltage/frequency) to further optimize the system. Both spaces are infeasible for exhaustive search typically leading to heuristic optimization algorithms that find some tradeoff between design quality and computational overhead. Machine learning (ML) can build powerful models that have successfully been employed in related domains. In this survey, we categorize how ML may be used and is used for design-time and run-time optimization and exploration strategies of ICs. A metastudy of published techniques unveils areas in computer-aided design (CAD) that are well explored and underexplored with ML, as well as trends in the employed ML algorithms. We present a comprehensive categorization and summary of the state of the art on ML for CAD. Finally, we summarize the remaining challenges and promising open research directions.

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“…Prautsch et al [2016] focuses on building design environments to foster reuse by organizing design-specific generators in a holistic framework, while the design entries are abstracted in higher levels rather than in device templates. Kunal et al [2019], Dhar et al [2021] combine the rule-based and template-based approaches to produce the templates and grids from a basic set of design rules with additional automated placement and routing capabilities for further productivity enhancements. Recent researches utilize machine-learning techniques (Dhar et al [2021], Chen et al [2021]) or open-source toolchains (Guthaus et al [2016], Ajayi et al [2019], Shalan and Edwards [2020]) to enhance design productivity in CMOS logic technologies with template-based layout generation methods.…”

Section: Prior Work On Layout Generationmentioning

confidence: 99%

“…The most critical requirement on layout generation methodologies is the encapsulation of design rules, of which complexity increases significantly as the process scales down. The most common approach to abstract the design rules is the use of templates and grids , Castro-López et al [2003], Castro-Lopez et al [2008], Prautsch et al [2016], Chang et al [2018], Kunal et al [2019], Dhar et al [2021]). The templates implement primitive physical elements such as transistors, resistors, and capacitors.…”

Section: Major Features To Implement Automatic Layout Generations In ...mentioning

confidence: 99%

A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids

Shin¹,

Lee²,

Kim³

et al. 2022

Preprint

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This paper presents an automatic layout generation framework in advanced CMOS technologies. The framework extends the template-and-grid-based layout generation methodology with the following additional techniques applied to produce optimal layouts more effectively. First, layout templates and grids are dynamically created and adjusted during runtime to serve various structural, functional, and design requirements. Virtual instances support the dynamic template-and-grid-based layout generation process. The framework also implements various post-processing functions to handle process-specific requirements efficiently. The post-processing functions include cut/dummy pattern generation and multiple-patterning adjustment. The generator description capability is enhanced with circular grid indexing/slicing and conditional conversion operators. The layout generation framework is applied to various design examples and generates DRC/LVS clean layouts automatically in multiple CMOS technologies.

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ALIGN: A System for Automating Analog Layout

Cited by 36 publications

References 15 publications

Analog Integrated Circuit Routing Techniques: An Extensive Review

Analog Integrated Circuit Routing Techniques: An Extensive Review

MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper

A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids

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