Algorithms for Multiplierless Multiple Constant Multiplication in Online Arithmetic

RECON: Resource-Efficient CORDIC-Based Neuron Architecture

“…It can be observed from the Table 5 that our proposed design has the least area as compared to other proposed designs [20]- [22]. While the design in [22] shows the least static and dynamic power, it requires more number of clock cycles along with a larger delay to compute the results as compared to our proposed design. Hence, our proposed design shows a lower power-delay-product (PDP) as compared to the design proposed in [22].…”

“…However, it is not scalable as increasing bitprecision for higher accuracy, leads to a substantial increase in the critical path and the propagation delay. In order to carry out inference for a deep neural network, the authors in [22], [27], [28] resort to a shift-and-add-based multiplication instead of bulky multipliers for MAC computation. Though the architecture was area and power-efficient, it suffered due to low throughput.…”

“…Though the architecture was area and power-efficient, it suffered due to low throughput. In [22], the authors proposed calculating one multiplication using shift and addition operation. The proposed approach requires n-shift left and n − 1 addition for n-bit precision calculation.…”

“…We compare our RECON architecture in MAC configuration with the state-of-the-art designs [20]- [22]. For RECON, the area of the corresponding module performing the MAC is shown in Fig.…”

“…6. For the sake of comparison, we have implemented the designs proposed in [20]- [22] with 8-bit precision at 45nm since they were proposed at different technology node. The post-synthesis performance parameters are populated in Table 5.…”