Algorithmic verification of logic controllers given as sequential function charts

Remelhe, Manuel; Lohmann, Sven; Stursberg, Olaf; Engell, Sebastian; Bauer, Nanette

doi:10.1109/cacsd.2004.1393850

Cited by 15 publications

(13 citation statements)

References 10 publications

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“…stochastic model checking (Kwiatkowska, Norman, & Parker, 2007). Timed model checking has been used, for example, by Remelhe et al (2004) and it is used in the current paper.…”

Section: Formal Verificationmentioning

confidence: 99%

“…With that in mind, the controller specification was developed in IEC 60848 SFC because it can then be used as both the starting point for the development of the timed automata to be verified with UPPAAL (Remelhe et al, 2004), and also the starting point for the development of the model of the controller using the StateGraphs Modelica library (Otter et al, 2005) for Simulation purposes (Seabra, Machado, Soares, Leão, & Silva, 2007).…”

Section: Formalism To Specify Controller Behaviourmentioning

confidence: 99%

“…In the Formal Verification of timed systems, several approaches can be used to increase the quality of the verification results. A distinction can be made between the work by Remelhe, Lohmann, Stursberg, and Engell (2004), where the translation of IEC 61131-3 Sequential Function Charts (SFC) into timed automata (Alur & Dill, 1990) is studied, and the work developed by Gaid, Bérard, and Smet (2005) where an approach for constructing the controller model is proposed. This latter work uses the initial approach proposed by Mader and Wupper (1999), and some work hypotheses related to the evolution of the controller model and time aspects, in order to increase the quality of Formal Verification results.…”

Section: Introductionmentioning

confidence: 98%

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Safe controllers design for industrial automation systems

Machado

Seabra

Campos

et al. 2011

Computers & Industrial Engineering

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a b s t r a c tThe design of safe industrial controllers is one of the most important domains related to Automation Systems research. To support it, synthesis and analysis techniques are available. Among the analysis techniques, two of the most important are Simulation and Formal Verification. In this paper these two techniques are used together in a complementary way. Understanding plant behaviour is essential for obtaining safe industrial systems controllers; hence, plant modelling is crucial to the success of these techniques. A two step approach is presented: first, the use of Simulation and, second, the use of Formal Verification of Industrial Systems Specifications. The specification and plant models used for each technique are described. Simulation and Formal Verification results are presented and discussed. The approach presented in the paper can be applied to real industrial systems, and obtain safe controllers for hybrid plants. The Modelica modelling language and Dymola simulation environment are used for Simulation purposes, and Timed Automata formalism and the UPPAAL real-time model-checker are used for Formal Verification purposes.

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“…stochastic model checking (Kwiatkowska, Norman, & Parker, 2007). Timed model checking has been used, for example, by Remelhe et al (2004) and it is used in the current paper.…”

Section: Formal Verificationmentioning

confidence: 99%

Section: Formalism To Specify Controller Behaviourmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

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Safe controllers design for industrial automation systems

Machado

Seabra

Campos

et al. 2011

Computers & Industrial Engineering

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“…The approach is illustrated for the example of a controlled batch evaporation system, as described in (Remelhe et al, 2004). The system consists of two tanks T1 and T2 with heaters, a condenser, and pipes to fill T1, to empty T1 into T2, to drain T2, and to transfer vapor from T1 into the condenser.…”

Section: Application To An Examplementioning

confidence: 99%

“…Since Sequential Functions Charts (SFC) become increasingly popular to specify industrial logic controllers, a number of recent investigations aim at making model checking applicable to SFC. While the approaches in (Bornot et al, 2000;Lampérière and Lesage, 2000) transform the SFC into (purely discrete) automata to apply verification subsequently, the methods in (L'Her et al, 1998;Remelhe et al, 2004;Bauer et al, 2004b) convert SFC into verifiable timed automata (TA), and thus make the inclusion of quantitative time into the analysis possible. The drawback of the latter method is, however, that the cyclic execution mode of PLC is explicitly transferred to the TA model, resulting in a rather complex model and thus a high verification effort (see Sec.…”

Section: Introductionmentioning

confidence: 99%

Improving Dependability of Logic Controllers by Algorithmic Verification

Stursberg

Lohmann

Engell

2005

IFAC Proceedings Volumes

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Functional safety, as addressed in the standard IEC 61508, is a key requirement for a high dependability of controlled systems. In order to guarantee that the function of programmable logic controllers (PLC) complies with given safety specifications, the use of verification has proven to be useful. This contribution builds upon a recently proposed approach to verify PLC programs with time specifications. It starts from a controller design given as sequential function chart (SFC), transforms the SFC into timed automata (TA), and applies model checking to verify (or falsify) functional safety. Since the explicit representation of the cyclic operation mode of PLC can lead to complex TA models, this paper investigates to which extent the cyclic mode can be omitted, to obtain simplified models for which the verification effort is considerably smaller.

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