Algorithmic methodologies for ultra-efficient inexact architectures for sustaining technology scaling

Lingamneni, Avinash; Muntimadugu, Kirthi Krishna; Enz, Christian; Karp, Richard M.; Palem, Krishna V.; Piguet, Christian

doi:10.1145/2212908.2212912

Cited by 39 publications

(37 citation statements)

References 22 publications

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“…An inexact fixed-point adder has been extensively studied and can be used in the exponent adder inexact adders such as lower-part-OR adders (LOA) [3], approximate mirror adders [4], approximate XOR/XNORbased adders, and equal segmentation adders [6], [7] can be found in the literature [1,2,3]. For a fast FP adder, a revised LOA adder is used, because it significantly reduces the critical path by ignoring the lower carry bits.…”

Section: Exponent Subtractormentioning

confidence: 99%

“…Inexact chips are smaller, faster and consume less energy. For inexact computing, fixed point arithmetic circuits have been already studied [2], [3], [4], [5], [6], [7], [8] as mentioned in the literature floating-point (FP) circuits consumes significantly more power due to its more complexity they have not been recommended for inexact computing. In computationally intensive applications FP format offers a large range dynamically.…”

Section: Introductionmentioning

confidence: 99%

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Design and Implementation of Low Power Inexact Floating Point Adder

Pedraj¹,

Kumar²

2017

IJCA

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Floating-point applications are a growing trend in the FPGA community. In nanoscale integrated circuits design as the demand for mobile computing & higher integration density is increasing power is becoming a very important constraint. Low-power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. For some applications where error is in tolerable range an inexact circuit offers reduction in both static and dynamic power .In this paper, an inexact floating-point adder is designed by approximating exponent sub tractor and mantissa adder. Related operations such as normalization and rounding are also dealt with in terms of inexact computing. It is then observed that it greatly reduced the power consumption and hence increased the reliability. KeywordsFloating-point adders, low power, high dynamic range image, inexact circuits, error analysis.

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Section: Exponent Subtractormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Low Power Inexact Floating Point Adder

Pedraj¹,

Kumar²

2017

IJCA

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“…This can be considered wasteful for multimedia applications where the inputs are inherently noisy and the targeted result of the application is a stochastic metric, e.g., maximization of the expected signal-to-noise-ratio for a coding system or the expected recall rate for a multimedia retrieval application. A few notable exceptions that have emerged in the last few years are: (i) the notion of stochastic processors [8], [9], [98], (ii) variable-precision hardware [103] or inexact design [93], [104] and (iii) stochastic logic [99]. In the first case, the hardware is deliberately under-designed or used beyond its safety margin via techniques such as voltage overscaling in order to produce occasional errors that are software-correctable.…”

Section: Error-tolerant Architecture Hardware Components and Crosmentioning

confidence: 99%

“…In the first case, the hardware is deliberately under-designed or used beyond its safety margin via techniques such as voltage overscaling in order to produce occasional errors that are software-correctable. In the second case, arithmetic hardware (typically multiply-accumulate units) is designed to have multiple precision levels [103]; alternatively, pruning techniques (using heuristics) are derived in order to remove computational units (blocks) according to their expected impact in the precision of the results [104]. In this way, errors affect the multimedia application in a controllable manner.…”

Section: Error-tolerant Architecture Hardware Components and Crosmentioning

confidence: 99%

Error Tolerant Multimedia Stream Processing: There's Plenty of Room at the Top (of the System Stack)

Andreopoulos

2013

IEEE Trans. Multimedia

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Abstract-There is a growing realization that the expected fault rates and energy dissipation stemming from increases in CMOS integration will lead to the abandonment of traditional system reliability in favor of approaches that offer reliability to hardware-induced errors across the application, runtime support, architecture, device and integrated-circuit (IC) layers. Commercial stakeholders of multimedia stream processing (MSP) applications, such as information retrieval, stream mining systems, and high-throughput image and video processing systems already feel the strain of inadequate system-level scaling and robustness under the always-increasing user demand. While such applications can tolerate certain imprecision in their results, today's MSP systems do not support a systematic way to exploit this aspect for cross-layer system resilience. However, research is currently emerging that attempts to utilize the error-tolerant nature of MSP applications for this purpose. This is achieved by modifications to all layers of the system stack, from algorithms and software to the architecture and device layer, and even the IC digital logic synthesis itself. Unlike conventional processing that aims for worst-case performance and accuracy guarantees, error-tolerant MSP attempts to provide guarantees for the expected performance and accuracy. In this paper we review recent advances in this field from an MSP and a system (layer-by-layer) perspective, and attempt to foresee some of the components of future cross-layer error-tolerant system design that may influence the multimedia and the general computing landscape within the next ten years.

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“…Different techniques such as logic minimization [6], simplified full adder cells [7] or speculative circuits [8] have recently been proposed. As a proof of concept, the first inexact adders (where full adder cells have been pruned from various adder architectures) have been fabricated [9] and measurements have demonstrated up to one order of magnitude savings. However, most of those techniques are based on manual designs or tweaks, and have not yet been integrated in the standard digital flow.…”

Section: Introductionmentioning

confidence: 99%

Design of energy-efficient discrete cosine transform using pruned arithmetic circuits

Schlachter

Camus

Enz

2016

2016 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-Inexact circuits and approximate computing have been gaining a lot of interest in order to improve performances and energy efficiency beyond the boundaries of conventional digital circuits. Image and video processing is one of the best candidate for applying such techniques. As one of the key building blocks, Discrete Cosine Transform (DCT) accelerators are investigated using pruned arithmetic circuits. A design methodology is presented in order to optimize both image quality and circuit performances. This work demonstrates that with such technique, savings are possible not only on arithmetic units, but in the entire accelerator hardware. Simulations show up to 12 % area and 10 % power savings with less than 20 dB PSNR degradation compared to the conventional DCT design.

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Algorithmic methodologies for ultra-efficient inexact architectures for sustaining technology scaling

Cited by 39 publications

References 22 publications

Design and Implementation of Low Power Inexact Floating Point Adder

Design and Implementation of Low Power Inexact Floating Point Adder

Error Tolerant Multimedia Stream Processing: There's Plenty of Room at the Top (of the System Stack)

Design of energy-efficient discrete cosine transform using pruned arithmetic circuits

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