Abstract:Many future embedded systems are likely to contain System-onChip solutions with on-chip networks and in order to achieve high aggregated throughputs in these networks, a switched topology can be used. For further performance improvements, the topology can be adapted to application demands, either when designing the chip or by run-time reconfiguration between different predefined application modes. In this paper, we present an algorithm for the choice of topology in, e.g., on-chip networks, considering realtime… Show more
“…OperaNP, a ReNoC-based platform, has been proposed by Elmiligi et al (2007) in which cores can be embedded on an array of programmable logic blocks while the data routing is done using another array of configurable routers. A topology allocation algorithm has been presented in Kunert et al (2007) Bartic et al (2003Bartic et al ( , 2005 which is scalable and can be changed to accommodate various needs of applications. This design is realized as part of the platform for reconfigurable systems.…”
This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. The authors and publishers have attempted to trace the copyright holders of all material reproduced in this publication and apologize to copyright holders if permission to publish in this form has not been obtained. If any copyright material has not been acknowledged please write and let us know so we may rectify in any future reprint.The Open Access version of this book, available at www.taylorfrancis.com, has been made available under a Creative Commons Attribution-Non Commercial-No Derivatives 4.0 license.
“…OperaNP, a ReNoC-based platform, has been proposed by Elmiligi et al (2007) in which cores can be embedded on an array of programmable logic blocks while the data routing is done using another array of configurable routers. A topology allocation algorithm has been presented in Kunert et al (2007) Bartic et al (2003Bartic et al ( , 2005 which is scalable and can be changed to accommodate various needs of applications. This design is realized as part of the platform for reconfigurable systems.…”
This book contains information obtained from authentic and highly regarded sources. Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. The authors and publishers have attempted to trace the copyright holders of all material reproduced in this publication and apologize to copyright holders if permission to publish in this form has not been obtained. If any copyright material has not been acknowledged please write and let us know so we may rectify in any future reprint.The Open Access version of this book, available at www.taylorfrancis.com, has been made available under a Creative Commons Attribution-Non Commercial-No Derivatives 4.0 license.
“…Some works [Stensgaard and Sparso 2008;Modarressi and Sarbazi-Azad 2007;Modarressi et al 2010Modarressi et al , 2011Avakian et al 2010;Wu et al 2011;Elmiligi et al 2007;Kunert et al 2007;Zheng et al 2010;Rana et al 2009; Bartic et al 2003Bartic et al , 2005Ahmed et al 2006] configure the network to meet application constraints. A reconfigurable NoC (ReNoC) architecture has been presented in Stensgaard and Sparso [2008] which enables the network topology to be configured by the application running on the SoC by using topology switches.…”
Section: Introductionmentioning
confidence: 99%
“…OperaNP, a reconfigurable NoC-based platform has been proposed in Elmiligi et al [2007] in which cores can be embedded on an array of programmable logic blocks while the data routing is done using another array of configurable routers. A topology allocation algorithm has been proposed in Kunert et al [2007] considering the demands of different applications. It selects topology depending on the application running on NoC.…”
This article proposes a reconfigurable Network-on-Chip (NoC) architecture based on mesh topology. It provides a local reconfiguration of cores to connect to any of the neighboring routers, depending upon the currently executing application. The area overhead for this local reconfiguration has been shown to be very small. We have also presented the strategy to map the cores of an application set onto this architecture. This has been achieved via a two-phase procedure. In the first phase, the cores of the combined application set are mapped tentatively to individual routers, minimizing the communication cost. In the second phase, for each application, positions of individual cores are finalized. A core gets attached to any neighbor of its tentative allocation. We have proposed Integer Linear Programming (ILP) formulation of both the phases. Since ILP takes large amount of CPU time, we have also formulated a Particle Swarm Optimization (PSO)-based solution for the two phases. A heuristic approach has also been developed for the reconfiguration. Comparison of communication cost, latency and network energy have been carried out for the applications, before and after reconfiguration. It shows significant improvement in performance via reconfiguration.
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