Algorithm-based low-power and high-performance multimedia signal processing

Liu, K.J.R.; Wu, An-Yeu; Raghupathy, A.; Chen, Jie

doi:10.1109/5.687834

Cited by 41 publications

(10 citation statements)

References 145 publications

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“…It is commonly used for audio and video processing, communication systems and transforms analysis. Different sampling rate can be obtained by _______________________________________________________________________________________ using upsampler and downsampler [3]. An Upsampler increasing the rate of previously sampled signal.…”

Section: Basic Operations Of Multirate Dspmentioning

confidence: 99%

To Develop and Implement Low Power High Speed VLSI for Processing Signals using Multirate Techniques

Rajendra¹

2015

IJRITCC

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Abstract:-Multirate technique is necessary for systems with different input and output sampling rates. Recent advances in mobile computing and communication applications demand low power and high speed VLSI DSP systems [4]. This Paper presents Multirate modules used for filtering to provide signal processing in wireless communication system. Many architecture developed for the design of low complexity, bit parallel Multiple Constant Multiplications operation which dominates the complexity of DSP systems. However, major drawbacks of present approaches are either too costly or not efficient enough. On the other hand, MCM and digit-serial adder offer alternative low complexity designs, since digit-serial architecture occupy less area and are independent of the data word length [1] [10]. Multiple Constant Multiplications is efficient way to reduce the number of addition and subtraction in polyphase filter implementation. This Multirate design methodology is systematic and applicable to many problems. In this paper, attention has given to the MCM & digit serial architecture with shifting and adding techniques that offers alternative low complexity in operations. This paper also focused on Multirate Signal Processing Modules using Voltage and Technology scaling. Reduction of power consumption is important for VLSI system and also it becomes one of the most critical design parameter. Transistorized Multirate module which has full custom design with different circuit topology and optimization level simulated on cadence platform. Multirate modules are used AMI 0.6 um, TSMC 0.35 um, and TSMC 0.25 um technologies for different voltage scaling. The presented methodology provides a systematic way to derive circuit technique for high speed operation at a low supply voltage. Multirate polyphase interpolator and decimator are also designed and optimized at architectural level in order to analyze the terms power consumption, area and speed.

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Section: Basic Operations Of Multirate Dspmentioning

confidence: 99%

To Develop and Implement Low Power High Speed VLSI for Processing Signals using Multirate Techniques

Rajendra¹

2015

IJRITCC

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“…We therefore focus on algorithm/architecture-level techniques to obtain low-power RS decoding. Various algorithm/architecture-level transformations [27]- [31] have been proposed in the literature. The transformations proposed include algebraic transformations [28] (such as associativity, distributivity, etc.…”

Section: The Algorithm/architecture-based Approachmentioning

confidence: 99%

“…), loop-unrolling/look ahead transformations [32] that try to break the recursive loops, retiming [27], folding/unfolding [33] transformations, and strength reduction [34]. These transformations can be used to obtain area-efficient high-speed or low-power designs [31], [35]- [37], depending on the design goal. One of the approaches to reduce the power consumption is to use these transformations to expose parallelism and enable pipelining in the computation.…”

Section: The Algorithm/architecture-based Approachmentioning

confidence: 99%

Algorithm-based low-power/high-speed Reed-Solomon decoder design

Raghupathy

Liu

2000

IEEE Trans. Circuits Syst. II

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Abstract-With the spread of Reed-Solomon (RS) codes to portable wireless applications, low-power RS decoder design has become important. This paper discusses how the Berlekamp Massey Decoding algorithm can be modified and mapped to obtain a low-power architecture. In addition, architecture level modifications that speed-up the syndrome and error computations are proposed. Then the VLSI architecture and design of the proposed low-power/high-speed decoder is presented. The proposed design is compared with a normal design that does not use these algorithm/architecture modifications. The power reduction when compared to the normal design is estimated. The results indicate a power reduction of about 40% or a speed-up of 1.34.

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“…Cosynthesis requires two central tasks -allocation of resources (e.g., programmable processors, FPGA devices, and so-called "algorithm-based" computing modules [38]), and scheduling of application actors onto the allocated resources. The scheduling task can be further subdivided into three main operations: assigning actors to processors, ordering actors on each processor, and determining the time at which each actor begins execution.…”

Section: Multiprocessor Scheduling Modelsmentioning

confidence: 99%

“…Let denote the subset of actors for which deadlines are specified; let denote the set of candidate allocations for a selected cluster; and let be the set of candidate allocations for which all actors in have their corresponding deadlines satisfied in the best case (i.e., according to ). If , then an allocation is chosen from the subset that maximizes the sum (38) of worst-case finish times over all actors for which pre-specified deadlines exist.…”

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confidence: 99%

Hardware/Software Cosynthesis of DSP Systems

Bhattacharyya¹

2001

Signal Processing and Communications

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This chapter focuses on the automated mapping of high level specifications of DSP applications into implementation platforms that employ programmable DSPs. Since programmable DSPs are often used in conjunction with other types of programmable processors, such as microcontrollers and general-purpose microprocessors, and with various types of hardware modules, such as FPGAs, and ASIC circuitry, this mapping task, in general, is one of cosynthesis -the joint synthesis of both hardware and software -for a heterogeneous multiprocessor.Since a large variety of cosynthesis techniques have been developed to date, it is not possible here to provide comprehensive coverage of the field. Instead, we focus on a subset of topics that are central to DSP-oriented cosynthesis -application modeling, hardware/software partitioning, synchronization optimization, and block-processing. Some important topics related to cosynthesis that are not covered here include memory management [1,11,26,37,53], which is discussed in Chapter 10; DSP code generation from procedural language specifications [39], which is the topic of Chapter 7; and performance analysis [36,49,54].Additionally, we focus on synthesis from coarse-grain dataflow models due to the increasing importance of such modeling in DSP design tools, and the ability of such modeling to expose valuable, high-level structure of DSP applications that is difficult to deduce from within compilers for general purpose programming models, and other types of models. Thus, we do not explore techniques for fine-grain cosynthesis [21], including synthesis of applicationspecific instruction processors (ASIPs) [43], nor do we explore cosynthesis for control-dominant systems, such as those based on procedural language specifications [22], communicating sequential processes [50], and finite state machine models [6]. All of these are important directions within cosynthesis research, but they do not fit centrally within the DSP-oriented scope of this chapter.

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Algorithm-based low-power and high-performance multimedia signal processing

Cited by 41 publications

References 145 publications

To Develop and Implement Low Power High Speed VLSI for Processing Signals using Multirate Techniques

To Develop and Implement Low Power High Speed VLSI for Processing Signals using Multirate Techniques

Algorithm-based low-power/high-speed Reed-Solomon decoder design

Hardware/Software Cosynthesis of DSP Systems

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