2020
DOI: 10.1039/d0ra00123f
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ALD Al2O3 gate dielectric on the reduction of interface trap density and the enhanced photo-electric performance of IGO TFT

Abstract: The amorphous indium gallium oxide thin film transistor was fabricated using a cosputtering method.

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Cited by 9 publications
(2 citation statements)
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References 23 publications
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“…For further verification of reduction for interfacial trap density, the hysteresis of the transfer curves was measured under gate voltage sweeping from -50 V to 50 V back and forth for ZnO and Si-ZnO 1/10 cases, which is shown in Figure S6 (SI). The large difference of hysteresis around the subthreshold region in ZnO indicates the high trap density between the insulator and active layer, while it is suppressed in Si-ZnO 1/10, which means that the device drives faster and has an energy-saving effect [66].…”
Section: Xps Resultsmentioning
confidence: 99%
“…For further verification of reduction for interfacial trap density, the hysteresis of the transfer curves was measured under gate voltage sweeping from -50 V to 50 V back and forth for ZnO and Si-ZnO 1/10 cases, which is shown in Figure S6 (SI). The large difference of hysteresis around the subthreshold region in ZnO indicates the high trap density between the insulator and active layer, while it is suppressed in Si-ZnO 1/10, which means that the device drives faster and has an energy-saving effect [66].…”
Section: Xps Resultsmentioning
confidence: 99%
“…A low SS can help turn on the device faster with a low voltage difference. In this study, the device SS reduces with anion/cation codoping, attributable to the decrease in the interfacial trap density (N it ) around the semiconductor-insulator interface according to the following relation [61]:…”
Section: Conditionmentioning
confidence: 99%