“…We believe that the etch-stop layer preserves the intact p-GaN surface, thereby preventing early breakdown of the device caused by impact ionization. These degradations are expected to be further mitigated by the p-GaN surface reinforcement process, involving several treatments before the gate electrode deposition and the use of refractory metal for the gate [27][28][29][30].…”
High-temperature operation of the p-GaN gate high-electron-mobility transistor (HEMT) was investigated, specifically up to 500 °C. The p-GaN gate HEMT demonstrated stable behavior with normally-off operation, steep increase of drain current in the subthreshold region, and suppressed off-state current. By adding Al2O3 etch-stop layer, the device showed significant reduction in subthreshold swing when measured at 500 °C, effectively mitigating hysteresis in the transfer characteristics. Additionally, the lifetime of the gate stack with the etch-stop layer was estimated to be much longer than that of the stack without the etch-stop layer. Through the integration of the depletion-mode (D-mode) metalinsulator-semiconductor HEMT (MIS-HEMT) device with the p-GaN gate device, a direct-coupled field-effect transistor logic (DCFL) inverter was fabricated. This inverter showed stable logic operation up to 500 °C, featuring rail-to-rail operation and large gain. A long-term reliability test conducted at 500 °C for 100 hours revealed stabilized onstate and off-state values after about 50 hours of operation.
“…We believe that the etch-stop layer preserves the intact p-GaN surface, thereby preventing early breakdown of the device caused by impact ionization. These degradations are expected to be further mitigated by the p-GaN surface reinforcement process, involving several treatments before the gate electrode deposition and the use of refractory metal for the gate [27][28][29][30].…”
High-temperature operation of the p-GaN gate high-electron-mobility transistor (HEMT) was investigated, specifically up to 500 °C. The p-GaN gate HEMT demonstrated stable behavior with normally-off operation, steep increase of drain current in the subthreshold region, and suppressed off-state current. By adding Al2O3 etch-stop layer, the device showed significant reduction in subthreshold swing when measured at 500 °C, effectively mitigating hysteresis in the transfer characteristics. Additionally, the lifetime of the gate stack with the etch-stop layer was estimated to be much longer than that of the stack without the etch-stop layer. Through the integration of the depletion-mode (D-mode) metalinsulator-semiconductor HEMT (MIS-HEMT) device with the p-GaN gate device, a direct-coupled field-effect transistor logic (DCFL) inverter was fabricated. This inverter showed stable logic operation up to 500 °C, featuring rail-to-rail operation and large gain. A long-term reliability test conducted at 500 °C for 100 hours revealed stabilized onstate and off-state values after about 50 hours of operation.
We demonstrated 500 °C operation of field-effect transistors made using ultra-wide bandgap semiconductor β-Ga2O3. Metal–semiconductor field-effect transistors were fabricated using epitaxial conductive films grown on an insulating β-Ga2O3 substrate, TiW refractory metal gates, and Si-implanted source/drain contacts. Devices were characterized in DC mode at different temperatures up to 500 °C in vacuum. These variable-temperature measurements showed a reduction in gate modulation of the drain current due to an increase in gate leakage across the gate/semiconductor Schottky barrier. Devices exhibited a reduction in transconductance with increasing temperature; despite this, drain current increased with temperature due to a reduction in threshold voltage caused by the de-trapping of electrons from deep-level traps. Devices also showed negligible change in semiconductor epitaxy and source/drain contacts, hence demonstrated recovery to their room-temperature electrical properties after the devices were tested intermittently at different high temperatures in vacuum. The mechanism of gate leakage was also explored, which implicated the presence of different conduction mechanisms at different temperatures and gate electric fields.
This Letter reports the device and material investigations of enhancement-mode p-GaN-gate AlGaN/GaN high electron mobility transistors (HEMTs) for Venus exploration and other harsh environment applications. The GaN transistor in this work was subjected to prolonged exposure (11 days) in a simulated Venus environment (460 °C, 94 bar, complete chemical environment including CO2/N2/SO2). The mechanisms affecting the transistor performance and structural integrity in harsh environment were analyzed using a variety of experimental, simulation, and modeling techniques, including in situ electrical measurement (e.g., burn-in) and advanced microscopy (e.g., structural deformation). Through transistor, Transmission Line Method (TLM), and Hall-effect measurements vs temperature, it is revealed that the mobility decrease is the primary cause of reduction of on-state performance of this GaN transistor at high temperature. Material analysis of the device under test (DUT) confirmed the absence of foreign elements from the Venus atmosphere. No inter-diffusion of the elements (including the gate metal) was observed. The insights of this work are broadly applicable to the future design, fabrication, and deployment of robust III-N devices for harsh environment operation.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.