Airgap Interconnects: Modeling, Optimization, and Benchmarking for Backplane, PCB, and Interposer Applications

Kumar, Vachan; Sharma, Rohit; Uzunlar, Erdal; Zheng, Li; Bashirullah, Rizwan; Kohl, Paul A.; Bakir, Muhannad S.; Naeemi, Azad

doi:10.1109/tcpmt.2014.2326798

Cited by 31 publications

(6 citation statements)

References 43 publications

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“…Packages for future, high-performance IC packages are especially challenged because of the simultaneous demand for a reduction in energy per bit and an increase in signal speed. Kumar et al modeled the performance gains of embedded air cavities in organic IC packages [11]. They found that the optimal bandwidth density (bits per second/interconnect width) with an air-cavity interposer could be increased by as much as 70Â compared to an organic PCB.…”

Section: Introductionmentioning

confidence: 99%

Decomposable and Template Polymers: Fundamentals and Applications

Uzunlar

Schwartz

Phillips

et al. 2016

Journal of Electronic Packaging

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Polymers can be used as temporary place holders in the fabrication of embedded air gaps in a variety of electronic devices. Embedded air cavities can provide the lowest dielectric constant and loss for electrical insulation, mechanical compliance in devices where low-force deformations are desirable, and can temporarily protect movable parts during processing. Several families of polymers have been used as sacrificial, templating polymers including polycarbonates, polynorbornenes (PNBs), and polyaldehydes. The families can be distinguished by chemical structure and decomposition temperature. The decomposition temperature ranges from over 400 °C to below room temperature in the case of low ceiling temperature polymers. Overcoat materials include silicon dioxide, polyimides, epoxy, and bis-benzocyclobutene (BCB). The methods of air-gap fabrication are discussed. Finally, the use of photoactive compounds in the patterning of the sacrificial polymers is reviewed.

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Section: Introductionmentioning

confidence: 99%

Decomposable and Template Polymers: Fundamentals and Applications

Uzunlar

Schwartz

Phillips

et al. 2016

Journal of Electronic Packaging

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“…Based on most recent on-chip interconnect and PCB interconnect studies in [43], [44], 40fJ/bit/mm for on-chip interconnect and 30pJ/bit/cm for PCB interconnect are used as I/O overhead. For core-memory distance, 10mm is assumed for on-chip case and 10cm is assumed for PCB trace length, both according to [43], [44]. Table III compares ELM-SR in both proposed in-memory computing platform and GPP platforms.…”

Section: System Level Evaluation Of Domain-wall Logic and Memorymentioning

confidence: 99%

An Energy-Efficient Nonvolatile In-Memory Computing Architecture for Extreme Learning Machine by Domain-Wall Nanowire Devices

Wang

et al. 2015

IEEE Trans. Nanotechnology

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The data-oriented applications have introduced increased demands on memory capacity and bandwidth, which raises the need to rethink the architecture of the current computing platforms. The logic-in-memory architecture is highly promising as future logic-memory integration paradigm for high throughput data-driven applications. From memory technology aspect, as one recently introduced non-volatile memory (NVM) device, domain-wall nanowire (or race-track) not only shows potential as future power efficient memory, but also computing capacity by its unique physics of spintronics. This paper explores a novel distributed in-memory computing architecture where most logic functions are executed within the memory, which significantly alleviates the bandwidth congestion issue and improves the energy efficiency. The proposed distributed in-memory computing architecture is purely built by domain-wall nanowire, i.e. both memory and logic are implemented by domain-wall nanowire devices. As a case study, neural network based image resolution enhancement algorithm, called DW-NN, is examined within the proposed architecture. We show that all operations involved in machine learning on neural network can be mapped to a logic-in-memory architecture by non-volatile domain-wall nanowire. Domain-wall nanowire based logic is customized for in machine learning within image data storage. As such, both neural network training and processing can be performed locally within the memory. The experimental results show that the domain-wall memory can reduce 92% leakage power and 16% dynamic power compared to main memory implemented by DRAM; and domainwall logic can reduce 31% both dynamic and 65% leakage power under the similar performance compared to CMOS transistor based logic. And system throughput in DW-NN is improved by 11.6x and the energy efficiency is improved by 56x when compared to conventional image processing system. 1536-125X (c)

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“…Hardware-based accelerator is currently practiced to assist machine learning. In traditional hardware accelerator, there is intensive data migration between memory and logic [Kumar et al 2014;Park et al 2013] caused both bandwidth and power walls. Therefore, for data-oriented computation, it is beneficial to place logic accelerators as close as possible to the memory to alleviate the I/O communication overhead .…”

Section: Introductionmentioning

confidence: 99%

Distributed In-Memory Computing on Binary RRAM Crossbar

Huang

Liu

et al. 2017

J. Emerg. Technol. Comput. Syst.

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The recently emerging resistive random-access memory (RRAM) can provide nonvolatile memory storage but also intrinsic computing for matrix-vector multiplication, which is ideal for the low-power and high-throughput data analytics accelerator performed in memory. However, the existing RRAM crossbar--based computing is mainly assumed as a multilevel analog computing, whose result is sensitive to process nonuniformity as well as additional overhead from AD-conversion and I/O. In this article, we explore the matrix-vector multiplication accelerator on a binary RRAM crossbar with adaptive 1-bit-comparator--based parallel conversion. Moreover, a distributed in-memory computing architecture is also developed with the according control protocol. Both memory array and logic accelerator are implemented on the binary RRAM crossbar, where the logic-memory pair can be distributed with the control bus protocol. Experimental results have shown that compared to the analog RRAM crossbar, the proposed binary RRAM crossbar can achieve significant area savings with better calculation accuracy. Moreover, significant speedup can be achieved for matrix-vector multiplication in neural network--based machine learning such that the overall training and testing time can be both reduced. In addition, large energy savings can be also achieved when compared to the traditional CMOS-based out-of-memory computing architecture.

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Airgap Interconnects: Modeling, Optimization, and Benchmarking for Backplane, PCB, and Interposer Applications

Cited by 31 publications

References 43 publications

Decomposable and Template Polymers: Fundamentals and Applications

Decomposable and Template Polymers: Fundamentals and Applications

An Energy-Efficient Nonvolatile In-Memory Computing Architecture for Extreme Learning Machine by Domain-Wall Nanowire Devices

Distributed In-Memory Computing on Binary RRAM Crossbar

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