Aging-Aware Power or Frequency Tuning With Predictive Fault Detection

Pachito, J.; Martins, C. V.; Vazquez, J. C.; Jacinto, Bruno; Teixeira, I.C.; Teixeira, J.P.; Champac, Victor; Semião, J.; Santos, M.B.

doi:10.1109/mdt.2012.2206009

Cited by 13 publications

(1 citation statement)

References 9 publications

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“…In this thesis, we focus on NBTI, as it has the most dominant long term effect in sub-90 nm CMOS process technologies [16]. NBTI is also the primary parametric failure mechanism in modern ICs [4] and a dominant aging mechanism causing PMOS threshold voltage degradation over time [1] resulting in increased delay.…”

Section: Nbtimentioning

confidence: 99%

An online wear state monitoring methodology for off-the-shelf embedded processors

Arunachalam

Chantem

Dick

et al. 2015

2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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The continued scaling of transistors has led to an exponential increase in on-chip power density, which has resulted in increasing temperature. In turn, the increase in temperature directly leads to the increase in the rate of wear of a processor. Negative-bias temperature instability (NBTI) is one of the most dominant integrated circuit (IC) failure mechanisms [5,13] that strongly depends on temperature. NBTI manifests in the form of increased circuit delays which can lead to timing failures and processor crashes. The ability to monitor the wear progression of a processor due to NBTI is valuable when designing real-time embedded systems. While NBTI can be detected using wear state sensors, not all chips are equipped with these sensors because detecting wear due to NBTI requires modifications to the chip design and incurs area and power overhead. NBTI sensor data may also not be exposed to users in software. In addition, wear sensors cannot take into account variations in wear due to the differences in the wear sensor devices and the other functional devices and their operating conditions. In this thesis, I propose a lightweight, online methodology to monitor the wear process due to NBTI for off-the-shelf embedded processors. Our proposed method requires neither data on the threshold voltage and critical paths nor additional hardware.Our methodology can also be extended to predict the wear progression due to some other dominant IC failure mechanisms. Experiments on embedded processors provide insights on iv NBTI wear progression over time. This knowledge can be used to design real-time embedded systems that explicitly consider runtime wear progression to increase predictability and maintain lifetime reliability requirements. In turn, the increase in temperature directly leads to the increase in the rate of wear of a processor. Negative-bias temperature instability (NBTI) is one of the most dominant integrated circuit (IC) failure mechanisms [5,13] that strongly depends on temperature.NBTI manifests in the form of increased circuit delays which can lead to the processor not meeting its timing constraints and result in processor crashes. The ability to monitor the wear progression of a processor due to NBTI is valuable when designing real-time embedded systems. Real-time embedded systems are systems whose tasks are performed correctly and in a timely manner and predictable manner. While NBTI can be detected using wear state sensors, not all chips are equipped with these sensors because detecting wear due to NBTI requires modifications to the chip design and incurs area and power overhead. NBTI sensor data may also not be exposed to users in software. In addition, wear sensors cannot take into account variations in wear due to the differences in the wear sensor devices and the other functional devices and their operating conditions. In this thesis, we propose a vi lightweight, online methodology to monitor the wear process due to NBTI for off-the-shelf embedded processors. Our proposed method requires neither diffi...

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Section: Nbtimentioning

confidence: 99%