AFTER, an ASIC for the Readout of the Large T2K Time Projection Chambers

Baron, P.; Calvet, D.; Delagnes, É.; Broïse, Xavier de la; Delbart, A.; Druillole, F.; Mazzucato, E.; Monmarthe, E.; Pierre, F.; Zito, M.

doi:10.1109/tns.2008.924067

Cited by 118 publications

(58 citation statements)

References 6 publications

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“…The bulk Micromegas prototypes were read out using the T2K/ TPC FEE based on the AFTER ASIC chip [8]. The AFTER chip, built in a 0:35 mm CMOS AMS process, houses 72 detector channels.…”

Section: The Tpc Experimental Setupmentioning

confidence: 99%

Large bulk Micromegas detectors for TPC applications

Anvar

Baron

Boyer

et al. 2009

Nuclear Instruments and Methods in Physics Research Section A:

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“…The bulk Micromegas prototypes were read out using the T2K/ TPC FEE based on the AFTER ASIC chip [8]. The AFTER chip, built in a 0:35 mm CMOS AMS process, houses 72 detector channels.…”

Section: The Tpc Experimental Setupmentioning

confidence: 99%

Large bulk Micromegas detectors for TPC applications

Anvar

Baron

Boyer

et al. 2009

Nuclear Instruments and Methods in Physics Research Section A:

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“…These devices have been used as low-power substitutes for flash ADCs for the past 25 years; some of the most representative examples are described in references [12][13][14][15][16][17][18][19]. SCA channels are the basic building blocks of the presented ASIC architecture, so a general descrip-120 tion is included here first.…”

Section: Analog Memory Asicmentioning

confidence: 99%

Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC

Aliaga

Bosch

Capra

et al. 2015

Nuclear Instruments and Methods in Physics Research Section A:

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The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. Its readout system is to be based on analog memory ASICs with 64 channels each that sample a 1 µs window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the total number of storage cells, particularly for large amounts of input channels. This is accomplished by partitioning the typical Switched Capacitor Array structure into two pipelined, asymmetric stages and introducing FIFO queue-like control circuitry for captured data, achieving total independence between the capture and readout operations.

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“…The amplification is performed with a ''bulk'' micromegas mesh [13], the signal collected by two orthogonal strip sets, and digitized with a chip [14] developed for T2K [15].…”

Section: The Present ''Ground'' Phase Of the Projectmentioning

confidence: 99%