Affine Coordinate Binary Edwards Curve Scalar Multiplier with Side Channel Attack Resistance

Fournaris, Apostolos P.; Koufopavlou, O.

doi:10.1109/dsd.2015.120

Cited by 10 publications

(18 citation statements)

References 15 publications

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“…Therefore, it is important to mention that this article mainly considers BHC architectures for discussion. Nevertheless, for the sake of completeness, some interesting hardware accelerators for the BEC model are also discussed [8,[23][24][25].…”

Section: Existing Fpga Architectures and Limitationsmentioning

confidence: 99%

“…Another BEC architecture, reported in [24], consumes 5919 FPGA slices on Virtex-5 FPGA. Similarly, the BEC architectures reported in [8,25] utilize 15804 and 6600 FPGA slices, respectively.…”

Section: Existing Fpga Architectures and Limitationsmentioning

confidence: 99%

“…It can be observed from the above discussion that the required hardware resources (FPGA slices) in existing FPGA implementations of BHC and BEC models are relatively higher [8,[18][19][20][21][22][23][24][25]. The architectures resulting higher hardware resources are not suitable for area constrained applications such as Identity-Based Encryption [15], WSNs [16] and RFID [17].…”

Section: Existing Fpga Architectures and Limitationsmentioning

confidence: 99%

“…The architecture is modeled in Verilog (HDL) using the Xilinx ISE design tool. To provide a realistic and reasonable comparison with state of the art solutions, published in [8,[18][19][20][21][22][23][24][25], the proposed architecture is synthesized for various FPGA devices. For Virtex-4, Virtex-5, Virtex-6 and Virtex-7 devices, the utilized FPGA slices over GF (2 163 ) are 5302, 2412, 2982 and 3508, respectively.…”

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confidence: 99%

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AREEBA: An Area Efficient Binary Huff-Curve Architecture

et al. 2021

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Elliptic curve cryptography is the most widely employed class of asymmetric cryptography algorithm. However, it is exposed to simple power analysis attacks due to the lack of unifiedness over point doubling and addition operations. The unified crypto systems such as Binary Edward, Hessian and Huff curves provide resistance against power analysis attacks. Furthermore, Huff curves are more secure than Edward and Hessian curves but require more computational resources. Therefore, this article has provided a low area hardware architecture for point multiplication computation of Binary Huff curves over GF(2163) and GF(2233). To achieve this, a segmented least significant digit multiplier for polynomial multiplications is proposed. In order to provide a realistic and reasonable comparison with state of the art solutions, the proposed architecture is modeled in Verilog and synthesized for different field programmable gate arrays. For Virtex-4, Virtex-5, Virtex-6, and Virtex-7 devices, the utilized hardware resources in terms of hardware slices over GF(2163) are 5302, 2412, 2982 and 3508, respectively. The corresponding achieved values over GF(2233) are 11,557, 10,065, 4370 and 4261, respectively. The reported low area values provide the acceptability of this work in area-constrained applications.

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Section: Existing Fpga Architectures and Limitationsmentioning

confidence: 99%

Section: Existing Fpga Architectures and Limitationsmentioning

confidence: 99%

Section: Existing Fpga Architectures and Limitationsmentioning

confidence: 99%

mentioning

confidence: 99%

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AREEBA: An Area Efficient Binary Huff-Curve Architecture

et al. 2021

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“…The drawback of this simplification is that the protection against SSCAs described above is contradicted, thus raising the need for additional countermeasures. For a conversion to be performed from a BECṔ : (X, Y, Z) point in projective coordinates to the corresponding P : (x, y) affine point, the formula x = X/Z and y = Y/Z is used [15].…”

Section: Binary Edwards Curvesmentioning

confidence: 99%

Machine Learning Attacks and Countermeasures on Hardware Binary Edwards Curve Scalar Multipliers

Dimopoulos

Fournaris

Koufopavlou

2021

JSAN

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Machine Learning techniques have proven effective in Side Channel Analysis (SCA), enabling multiple improvements over the already-established profiling process of Template Attacks. Focusing on the need to mitigate their impact on embedded devices, a design model and strategy is proposed that can effectively be used as a backbone for introducing SCA countermeasures on Elliptic Curve Cryptography (ECC) scalar multipliers. The proposed design strategy is based on the decomposition of the round calculations of the Montgomery Power Ladder (MPL) algorithm and the Scalar Multiplication (SM) algorithm into the underlined finite field operations, and their restructuring into parallel-processed operation sets. Having as a basis the proposed design strategy, we showcase how advanced SCA countermeasures can be easily introduced, focusing on randomizing the projective coordinates of the MPL round’s ECC point results. To evaluate the design approach and its SCA countermeasures, several simple ML-based SCAs are performed, and an attack roadmap is provided. The proposed roadmap assumes attackers that do not have access to a huge number of leakage traces, and that have limited resources with which to mount Deep Learning attacks. The trained models’ performance reveals a high level of resistance against ML-based SCAs when including SCA countermeasures in the proposed design strategy.

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