AES-Based Cryptographic and Biometric Security Coprocessor IC in 0.18-μm CMOS Resistant to Side-Channel Power Analysis Attacks

Tiri, Kris; Hwang, D.; Hodjat, A.; Lai, Bo-Cheng; Yang, Shenglin; Schaumont, Patrick; Verbauwhede, Ingrid

doi:10.1109/vlsic.2005.1469370

Cited by 19 publications

(15 citation statements)

References 6 publications

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“…They only have a minimal influence on the design flow and a negligible overhead in design time. The additional steps required only a total of 6 min of central processing unit (CPU) time for our prototype IC implementing a high-throughput Advanced Encryption Standard (AES), controller, and fingerprint processor [37].…”

mentioning

confidence: 99%

A digital design flow for secure integrated circuits

Tiri

Verbauwhede

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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126

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mentioning

confidence: 99%

A digital design flow for secure integrated circuits

Tiri

Verbauwhede

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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126

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“…In the cell level, several techniques have been reported such as Sense Amplifier Based Logic (SABL) [5], Wave Dynamic Differential Logic (WDDL) [6], Three-phase Dual-rail Pre-charge Logic (TDPL) [7] and Pre-Charge Static Logic (PCSL) [8]. The concept of SABL is to balance internal charges by fully charging and discharging all internal node for different processed data (i.e.…”

Section: Wwwastesjcom 421mentioning

confidence: 99%

“…bit-0 or bit-1). However, during the implementation in crypto-device, the internal charges is not fully discharged at high frequency (>100MHz) due to small variation on the internal parasitic capacitance [6]. The WDDL and PCSL implement Pre-charge and Evaluation cycle with differential logic to make a constant power dissipation for different logic transition.…”

Section: Wwwastesjcom 421mentioning

confidence: 99%

“…In the AES-128 implementation, the WDDL occupies over 3.1× area, dissipate 3.7× dynamic power and 3.8× reduction in throughput compared with standard cell implementation [5]. For the PCSL implementation, the power dissipations tend to leak information during the pre-charge cycle [6] and hence vulnerable against CPA attack. The TDPL employs dual-rail dynamic logic with three-phase clocking system (Pre-charge, Evaluation and Discharge).…”

Section: Wwwastesjcom 421mentioning

confidence: 99%

“…The AES algorithm has been employed in a variety of security systems including the defense and banking applications since 2001 [6]. It is categorized as a symmetric-key encryption algorithm, in which the transmitter and receiver employ the same secret key for encryption and decryption respectively.…”

Section: Advanced Encryption Standardmentioning

confidence: 99%

See 2 more Smart Citations

A Highly-Secured Arithmetic Hiding cum Look-Up Table (AHLUT) based S-Box for AES-128 Implementation

Pammu¹,

Chong²,

Gwee³

2017

Adv. sci. technol. eng. syst. j.

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Design and Implementation of a Configurable Encryption System for Power-Constrained Devices

Rosa¹,

Murguı́a²,

Mejía-Carlos³

et al. 2023

IEEE Access

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In this work, we present a configurable encryption system based on the Encryption by Synchronization in a Cellular Automata (ESCA) system, which is a symmetric key algorithm based on the synchronization phenomenon of Cellular Automata with rule-90. With the aim of producing a flexible system to trade-off power consumption and security level, we implemented a pseudo-random number generator (PRNG) that can be configured with three different key sizes. This variable-length PRNG, together with the capability of bypassing specific modules in the rest of the system, allow us to operate under a wide range of applications. In particular, it would enable online adjustments in IoT and power-constrained devices to fine-tune them between a low-power consumption and a maximum-security level. The system can be implemented with 5956 gates, and it is designed to provide in a 0.5 µm CMOS process a throughput of 50 Mbps @ 37 mW, at the maximum-security level, and an energy consumption of less than 7 mW @ 30 Mbps at the lowest-security level, while still providing a satisfactory perceptual security metric.

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AES-Based Cryptographic and Biometric Security Coprocessor IC in 0.18-μm CMOS Resistant to Side-Channel Power Analysis Attacks

Cited by 19 publications

References 6 publications

A digital design flow for secure integrated circuits

A digital design flow for secure integrated circuits

A Highly-Secured Arithmetic Hiding cum Look-Up Table (AHLUT) based S-Box for AES-128 Implementation

Design and Implementation of a Configurable Encryption System for Power-Constrained Devices

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