AES and the cryptonite crypto processor

Oliva, Dino; Buchty, Rainer; Heintze, Nevin

doi:10.1145/951710.951738

Cited by 14 publications

(4 citation statements)

References 2 publications

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“…As described in Fig. 6, the performance of AES is 256Mbits/s, which is faster than Hifn7854 [9] and is analogous to many other outstanding machines. The test chip has only about 32k core gates and a very low power consumption of about 70mW under 60MHz.…”

Section: D-10mentioning

confidence: 87%

A low-cost cryptographic processor for security embedded system

Han

Zeng

et al. 2008

2008 Asia and South Pacific Design Automation Conference

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Abstract-A low-cost cryptographic processor for security embedded system is presented in this paper. The processor, without any assistance of dedicated cryptographic coprocessors, is scalable and very efficient for popular cryptographic algorithms such as RSA/ECC, AES, Hash, etc. Based on SMIC 0.18um standard CMOS technology, the core circuit of the test chip has only about 32k gates, and a max frequency of 200MHz, under which the 1024-bit RSA algorithm takes only 150ms and the throughout of AES reaches 256Mbits/s.

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Section: D-10mentioning

confidence: 87%

A low-cost cryptographic processor for security embedded system

Han

Zeng

et al. 2008

2008 Asia and South Pacific Design Automation Conference

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“…The Cryptonite crypto-processor is a VLIW architecture with two 64-bit datapaths [14]. It features support for AES through a set of special instructions for performing byte-permutation, rotation and xor operations.…”

Section: Previous Work On Extensions For Aesmentioning

confidence: 99%

Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors

Tillich

Großschädl

2006

Lecture Notes in Computer Science

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Abstract. Secure communication over public networks like the Internet requires the use of cryptographic algorithms as basic building blocks. Most cryptographic workloads pose a considerable burden on devices like PDAs, cell phones, and sensor nodes, which are limited in processing power, memory and energy. In this paper we present an approach to increase the efficiency of 32-bit processors for handling symmetric cryptographic algorithms with the help of instruction set extensions. We propose a number of custom instructions to support the Advanced Encryption Standard (AES). Using the SPARC V8-compatible Leon2 embedded processor, we evaluate the effects of the extensions on performance and code size of AES, as well as on silicon area. With a moderate increase in silicon area, AES performance can be improved by a factor of nearly 10, while code size is reduced significantly and implementation flexibility is retained. We also show that our approach is very beneficial for implementation in superscalar processors and that it can compete with the performance of previously proposed cryptographic processors and instruction set extensions.

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“…Other solutions can be considered consisting of programmable hardware accelerators. In [11] and [12] the authors propose cryptography processor or co-processor which can perform various execution modes and achieve high throughput. However, they do not address the attack issue and the energy efficiency metric is not considered.…”

Section: Secure Embedded System Design Challengesmentioning

confidence: 99%

Reconfigurable Security Primitive for Embedded Systems

Gogniat

Wolf

Burleson

2005

2005 International Symposium on System-on-Chip

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Abstract-Embedded systems present significant security challenges due to their limited resources, power constraints and a variety of inherent vulnerabilities. In this paper, we propose a reconfigurable security primitive for secure embedded systems that leverages the capabilities of reconfigurable hardware to provide efficient and flexible architectural support to both security standards and a range of attacks. This paper stresses design challenges for secure embedded systems and argues the case for reconfigurable architectural support for security. The reconfigurable security primitive is based on two main ideas: 1) an adaptable datapath, and 2) a hierarchy of controllers at the primitive and system level. The first controller manages the performance policy while the second one deals with the security policy. The AES cryptography algorithm has been considered to show the benefit of our approach compared to hardware and software solutions.

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AES and the cryptonite crypto processor

Cited by 14 publications

References 2 publications

A low-cost cryptographic processor for security embedded system

A low-cost cryptographic processor for security embedded system

Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors

Reconfigurable Security Primitive for Embedded Systems

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