Advanced SystemBuilder: A tool set for multiprocessor design space exploration

Shibata, Seiya; Honda, Shinya; Tomiyama, Hiroyuki; Takada, Hiroaki

doi:10.1109/socdc.2010.5682967

Cited by 10 publications

(6 citation statements)

References 2 publications

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“…There were three architectures, "1Core-HW", "2Core-HW", and "3Core-HW", which have one, two, and three Nios II soft-core processors, respectively, and each architecture has dedicated HW. We evaluated the execution time and the HW area by implementing the mappings on FPGA with our system-level design tool [2]. An exhaustive search (ES), NSGA-II, and SPEA2 have been used for comparison [3].…”

Section: Introduction and Proposed Methodsmentioning

confidence: 99%

Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs

Ando¹,

Shibata²,

Honda³

et al. 2014

2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines

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This paper presents an efficient design-space exploration method to identify the Pareto solution for the relation between the execution time and the hardware area. Initially, our method takes a particular system mapping that is surely in the Pareto solution, and then repeats the local search and the update of the Pareto solution until the Pareto solution reaches a steady state. Compared to genetic-algorithm-based methods, we found that our method outputs the Pareto solution with a smaller number of explorations for larger design spaces.

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Section: Introduction and Proposed Methodsmentioning

confidence: 99%

Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs

Ando¹,

Shibata²,

Honda³

et al. 2014

2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines

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“…We divided AES description into five processes as shown in left side of Fig. 2 so that we can use our system-level design tool [10] and explore SW/HW partitioning. We just changed SW description to SW/HW mixed description.…”

Section: Initial Design Of Aes Encryption and Decryptionmentioning

confidence: 99%

Automated Identification of Performance Bottleneck on Embedded Systems for Design Space Exploration

Ando

Shibata

Honda

et al. 2013

IFIP Advances in Information and Communication Technology

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Abstract. Embedded systems usually have strict resource and performance constraints. Designers often need to improve the system design so that the system satisfies those constraints. In such case, performance bottlenecks should be identified and improved effectively. In this paper, we present a method to identify performance bottlenecks. Our method automatically identifies not only the bottlenecks but also a list of improvement rates of bottlenecks that is necessary for the system to satisfy design constraints. With the list of improvement rates, designers easily consider how to improve the bottlenecks. A case study on AES encryption and decryption application shows effectiveness of our method.

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“…In literature several approaches for automatic generation of drivers for HW/SW communication can be found [7,8]. In some early work [9] an automatic approach for the generation of application specific heterogeneous multi processor architectures has been proposed.…”

Section: Related Workmentioning

confidence: 99%

A framework for generic HW/SW communication using remote method invocation

Hartmann

Grüttner

Ittershagen

et al. 2011

2011 Electronic System Level Synthesis Conference (ESLsyn)

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Implementation of communication between different tasks of a concurrent embedded system is a challenging problem. The aim of our work is to support the refinement and relocation of tasks onto different execution units, such as processors running different operating system or even dedicated hardware. For this purpose communication should be transparent and as independent as possible from the underlying middleware or embedded operating system. Moreover, communication should also be transparent accros the HW/SW boundary.In this work we present a generic framework for seamless communication of (software) tasks with shared resources, called Shared Objects. Communication is implemented using a method-based interface realizing a Remote Method Invocation (RMI) protocol. Our shared communication resources can either be implemented as dedicated hardware, as shared memory or local tasks. The presented framework is a first step towards the unification of shared resource access based on embedded Linux. The effectiveness of our approach is be evaluated with different task mappings and shared resource access implementation styles.

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Advanced SystemBuilder: A tool set for multiprocessor design space exploration

Cited by 10 publications

References 2 publications

Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs

Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs

Automated Identification of Performance Bottleneck on Embedded Systems for Design Space Exploration

A framework for generic HW/SW communication using remote method invocation

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