Advanced synchronous scan test methodology for multi clock domain ASICs

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

2007

Abstract-Even though many embedded cores contain several clock domains, most published methods for wrapper design have been limited to single-frequency cores. Cumbersome and invasive design techniques, such as insertion of test points, are needed to make these methods applicable to current-generation embedded cores. This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. The proposed 1500-compliant wrapper prevents clock skew and allows scan chains in different clock domains to shift test data at distinct clock frequencies, which enables a better control of power dissipation during test. We present an integer linear programming (ILP) model that can be used to minimize the core testing time under power constraints for small problem instances, and which can be combined with LP-relaxation to obtain lower bounds on the testing time for larger instances. We also present an efficient heuristic method that is applicable to large problem instances, and which yields the same (optimal) testing time as ILP for small problem instances.

Section: A Multifrequency At-speed Testingmentioning

confidence: 99%

Section: B Heuristic For Wrapper Optimizationmentioning

confidence: 99%

Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains

Nicolici

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

2007

“…In our experiments, we select NoWeights = 100 and normalWeight = 200 to limit the run time to a few seconds. Inside the inner loop (lines [8][9][10][11][12][13][14][15][16][17][18][19], the algorithm selects the shift frequency…”

Section: Heuristic For Wrapper Optimizationmentioning

confidence: 99%

“…In addition, several techniques [14,17] have been proposed to test designs with multiple clock domains. However, regardless of their effectiveness, these endeavors mainly consider testing at the chip level and they need to be adapted for testing corebased SOCs, which employ a "divide and conquer" test strategy at core level.…”

Section: Introductionmentioning

confidence: 99%

Multi-frequency wrapper design and optimization for embedded cores under average power constraints

Nicolici

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

2005

This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed method improves upon a recent wrapper design method that requires a common shift frequency for the scan elements in the different clock domains. We present an integer linear programming (ILP) model that can be used to minimize the testing time for small problem instances. We also present an efficient heuristic method that is applicable to large problem instances, and which yields the same (optimal) testing time as ILP for small problem instances. Compared to recent work on wrapper design using a single shift frequency, we obtain lower testing times and the reduction in testing time is especially significant under power constraints.

“…Today's heterogeneous SoCs consist of embedded cores that not only operate in multiple clock domains [Goel et al 2004;Lin and Thompson 2003;Schmid and Knablein 1999], but also (due to differences in performance levels, design styles, and scan insertion methods) differ in their maximum scan clock frequencies [Vranken et al 2003]. The difference in scan clock frequencies between embedded cores can also arise due to the integration of various cores derived from different, older-generation SoCs into a single, current-generation SoC [Chickermane et al 2001].…”

Section: Introductionmentioning

confidence: 99%

Power-aware SoC test planning for effective utilization of port-scalable testers

Sehgal

Bahukudumbi

ACM Trans. Des. Autom. Electron. Syst.

2008

Many system-on-chip (SoC) integrated circuits contain embedded cores with different scan frequencies. To better meet the test requirements for such heterogeneous SoCs, leading tester companies have recently introduced port-scalable testers, which can simultaneously drive groups of channels at different data rates. However, the number of tester channels available for scan testing is limited; therefore, a higher shift frequency can increase the test time for a core if the resulting test access architecture reduces the bit-width used to access it. We present a scalable test planning technique that exploits port scalability of testers to reduce SoC test time. We compare the proposed heuristic optimization method to two baseline methods based on prior works that use a single scan data rate for all embedded cores. We also propose a power-aware test planning technique to effectively utilize port-scalable testers under constraints of test power consumption. Experimental results are presented for power-aware test scheduling to illustrate the impact of power constraints on overall test time.