Advanced safety test solution for automotive SoC based on In-System-Test architecture

Im, Sangsoon; Nam, Giha; Park, Sungcheol; Noh, Mijung

doi:10.1109/iscas48785.2022.9937235

Cited by 3 publications

(5 citation statements)

References 8 publications

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“…Im et al [13] presented an architecture for automotive SOC which supports in-field testing. The architecture includes power-on self-test (POST) and in-system test (IST) controller blocks that interface with advanced peripheral bus (APB), as shown in Figure 3.…”

Section: Testing Methodologies 41 In-field Testingmentioning

confidence: 99%

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Testing nanometer memories: a review of architectures, applications, and challenges

Sontakke,

Atchina

2024

IJECE

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Newer defects in memories arising from shrinking manufacturing technologies demand improved memory testing methodologies. The percentage of memories on chips continues to rise. With shrinking technologies (10 nm up to 1.8 nm), the structure of memories is becoming denser. Due to the dense structure and significant portion of a chip, the nanometer memories are highly susceptible to defects. High-frequency specifications, the complexity of internal connections, and the process variation due to newer manufacturing technology further increased the probability of the physical failure of memories to a great extent. Memories need to be defect-free for the chip to operate successfully. Therefore, testing embedded memories has become crucial and is taking significant test costs. Researchers have proposed multiple approaches considering these factors to test the nanometer memories. They include using new fault models, march algorithms, memory built-in self-test (MBIST) architectures, and validation strategies. This paper surveys the methodologies presented in recent times. It discusses the core principles used in them, along with benefits. Finally, it discusses key opens in each and offers the scope for future research.

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Section: Testing Methodologies 41 In-field Testingmentioning

confidence: 99%

“…Figure 4 shows the sequence of operations being performed during in-field usage using architecture in [13]. First, the POST controller initiates a memory test during power-up and boot flow.…”

Section: Testing Methodologies 41 In-field Testingmentioning

confidence: 99%

Testing nanometer memories: a review of architectures, applications, and challenges

Sontakke,

Atchina

2024

IJECE

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“…A design-for test (DFT) architecture supporting memory repair during power-on and the in-system test is presented in [19]. At the start of power on, repair data from the manufacturing stage is loaded from onetime programmable (OTP) memory in BISR chains.…”

Section: In-field Repairmentioning

confidence: 99%

“…Figure 11. Parallel for faulty element replacement with redundant element [54] Im et al [19] proposed using multiple BISR controllers and accessing fuse data in parallel. This approach helps in 2 ways.…”

Section: Improving Repair Operation Clock Frequencymentioning

confidence: 99%

Memory built-in self-repair and correction for improving yield: a review

Sontakke,

Atchina

2024

IJECE

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Nanometer memories are highly prone to defects due to dense structure, necessitating memory built-in self-repair as a must-have feature to improve yield. Today’s system-on-chips contain memories occupying an area as high as 90% of the chip area. Shrinking technology uses stricter design rules for memories, making them more prone to manufacturing defects. Further, using 3D-stacked memories makes the system vulnerable to newer defects such as those coming from through-silicon-vias (TSV) and micro bumps. The increased memory size is also resulting in an increase in soft errors during system operation. Multiple memory repair techniques based on redundancy and correction codes have been presented to recover from such defects and prevent system failures. This paper reviews recently published memory repair methodologies, including various built-in self-repair (BISR) architectures, repair analysis algorithms, in-system repair, and soft repair handling using error correcting codes (ECC). It provides a classification of these techniques based on method and usage. Finally, it reviews evaluation methods used to determine the effectiveness of the repair algorithms. The paper aims to present a survey of these methodologies and prepare a platform for developing repair methods for upcoming-generation memories.

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“…Here, 𝑃 represents the initial population of the Namib beetle. The population of beetles for the objective function is evaluated and expressed in (13).…”

Section: Bisrmentioning

confidence: 99%

ADKNN fostered BIST with Namib Beetle optimization algorithm espoused BISR for SoC-based devices

Alnatheer,

Ahmed

2024

IJEECS

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Redundancy analysis is a widely used method in fault-tolerant memory systems, and it is essential for large-size memories. In current security operations centers (SoCs), memory occupies most of the chip space. To correct these memories using a conventional external equipment test approach is more difficult. To overcome this issue, memory creators utilize redundancy mechanism for substituting the columns and rows along with a spare one to increase output of the memories. In this study, a built-in-self-test (BIST) to test memories and built-in-self-repair (BISR) mechanism to repair the faulty cells for any recent SoC devices is proposed. The BIST, based on adaptive activation functions with a deep Kronecker neural network (ADKNN), not only detects the defect but also determines the kind of defect. The BISR block uses the Namib Beetle optimization algorithm (NBOA) to fix the mistakes in the memory under test (MUT). The study attempts to determine how the characteristics of SoC-based devices change in the real world and then contributes to the suggested controller blocks. Performance metrics such as slice register, region, delay, maximum operating frequency, power consumption, minimum clock period, and access time evaluate performance. Comparing the proposed ADKNN-NBOA-BIST-BISR scheme to existing BIST, BISR, and BISD-based methods reveals its significant performance.

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Advanced safety test solution for automotive SoC based on In-System-Test architecture

Cited by 3 publications

References 8 publications

Testing nanometer memories: a review of architectures, applications, and challenges

Testing nanometer memories: a review of architectures, applications, and challenges

Memory built-in self-repair and correction for improving yield: a review

ADKNN fostered BIST with Namib Beetle optimization algorithm espoused BISR for SoC-based devices

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