2014 International Conference on High Performance Computing &Amp; Simulation (HPCS) 2014
DOI: 10.1109/hpcsim.2014.6903697
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Advanced Pattern based Memory Controller for FPGA based HPC applications

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Cited by 34 publications
(20 citation statements)
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“…2) Scratchpad Memory: A programmable and parameterizable Scratchpad Memory [3] architecture acts as a cache in the system. It accesses the whole data pattern as a cache line and temporarily holds data to speedup later accesses.…”
Section: A Memory Organizationmentioning
confidence: 99%
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“…2) Scratchpad Memory: A programmable and parameterizable Scratchpad Memory [3] architecture acts as a cache in the system. It accesses the whole data pattern as a cache line and temporarily holds data to speedup later accesses.…”
Section: A Memory Organizationmentioning
confidence: 99%
“…The static data structures are aligned in terms of memory addressing, managing data structures that have compile-time predictable and aligned data accesses. The irregular descriptor memory [3] holds information about unaligned dynamic data structures (tree-based) and their access patterns, where the descriptor memory is allocated during runtime. The size of the allocated memory can vary between executions of the program.…”
Section: B Data Structures and Access Descriptionmentioning
confidence: 99%
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“…MAPC uses the Pattern Descriptor Unit (PDU) to hold the information of complex memory access patterns in descriptors [7] [8]. The set of parameters for a descriptor block includes local address, base address, size, stride and offset (shown in Figure 2).…”
Section: B Pattern Descriptor Unitmentioning
confidence: 99%
“…2) Specialized Memory: The ViPS Specialized Memory [14] (SM) is directly connected to the Processing Unit and provides single cycle data access. Like a cache, the SM temporarily holds data to speed up later accesses.…”
Section: B Memory Unitmentioning
confidence: 99%