Advanced packaging technologies on 3D stacked LSI utilizing the micro interconnections and the layered microthin encapsulation

Abstract

The advanced 3D stacking technologies are discussed in this paper. They are the microbumping in 20µm pitch, the basic processes of the advanced bonding processes for the high precision and the reliable interconnections, the novel technologies to encapsulate the layered microthin gaps less than 10µm, and the non-destructive inspection. These technologies are confirmed to realize the 3D stacked LSI structure, and it will be expanded to the advanced system packaging technologies in the near future. IntroductionNowadays, the demand for the high-density electronics component is quite general for the consumer information equipment. The new packaging technologies are required to break through the limitation of the conventional package performance [1]. The developed 3D LSI has the through-hole copper electrodes in the Si devices, which are formed by the reactive ion etching (RIE) process in 20µm pitch for the vertical wiring retributions. The substantial technologies for the 3D stacked LSI are the hyperfine interconnections of the microbumps on the through-hole electrodes and the encapsulation of the narrow gaps through the layered devices. The established results for each essential technology are introduced respectively as following.

Heterogeneous 2.5D integration on through silicon interposer

“…As to the assembly, different metallurgical bonding processes have been developed, such as solid-liquid-inter diffusion method 58 and thermal compression method. 59,60 In IBM, Wright et al developed solder micro bumping technology. 61 Different solder materials, such as e-PbSn and CuSn systems, have been studied.…”

Low-Temperature Polymer-Based Three-Dimensional Silicon Integration

“…The dielectric layers separating the donor to the host layer's metallization consisted of interlevel dielectric and BOX from the donor layer (0.6 µm of SiO 2 ), 2 µm of BCB wafer bonding medium between device layers and 1 µm of SiO 2 in the host layer. After via window/hole patterning, RIE with CF 4 /O 2 was employed to etch SiO 2 layers in the donor, and the host wafer and SF 6 /O 2 chemistry was used to etch the BCB wafer bonding medium [8]. Commercially available Pad Etch wet enchant was employed in the final step to remove the residual SiO 2 .…”

“…With the initial attempts starting in 1980s, a number of techniques have been developed. Examples of early techniques include the use of polysilicon [4], recrystallization [5], [6], and microbumps [7], [8]. Each of these has its own advantages and disadvantages.…”

Three dimensional interconnects with through silicon vias and electroplating solder microbumps

“…It also provides shortest and high performance interconnections between chip to chip and chip to substrate. The medium of the connections is soldering micro bumps which are assembled on the chip and also provide interconnections between chips [1][2][3][4][5][6][7]. Therefore, flip chip assembly of solder micro bumps and TSVs is a critical step for 3D chip stacking.…”