Advanced Multifunctional Field Effect Devices Using Common Gate for Both 2D Transition‐Metal Dichalcogenide and InGaZnO Channels

Abstract

p-and n-channel FETs, homogeneous and heterogeneous complementary metal oxide semiconductor (CMOS) inverters have been reported. [15][16][17][18][19][20] Moreover, PN junction-and Schottky junction-based FETs were even reported using 2D TMD semiconductors. [21,22] However, in a practical view, devices based on only 2D materials are not easy to fabricate and seldom reproducible. Very recently, researchers have attempted other approaches combining 2D materials and conventionally proven ones to fabricate more practical type of classical devices such as CMOS inverters and hetero PN junction diodes. [23][24][25][26][27][28][29][30][31][32] Those could be regarded as practical approaches in consideration that one could use conventionally proven semiconductors for functional electron devices. However, such approaches are still very rare.In the present study, we approach to combine 2D n-/or p-TMD FET and conventional InGaZnO (IGZO) FET, presenting advanced non-classical functions: multivalue (MV) FETs for logic and photodetecting function, and signal frequency doubler. Multivalue logic would be important in the future for minimizing the power consumption which emerges as challenging issues in the present Si-based binary logic circuitry. [33][34][35] Frequency doubling is also an interesting and beneficial technique in alternating current (AC) circuit. [36,37] For these purposes, we have initially fabricated n-IGZO channel FET on glass substrate, which is followed by n-channel TMD (n-ReSe 2 , n-WSe 2 , p-, or ambipolar-MoTe 2 ) FETs. Although top-MoTe 2 /bottom-IGZO combination approach was once introduced for basic classical devices, [26] present study displays more advanced novel functions based on unique device architecture; we use a long and unique-shape gate pattern, so that n-or p-channel TMD and n-IGZO channels may be located side by side sharing a gate metal in common. Atomic layer deposited (ALD) Al 2 O 3 dielectric is located on the patterned gate. According to individual transfer characteristics of two FET devices, our n-IGZO FET always shows higher drain current (I D ) and more positive-side turn-on voltage (V t ) than those of n-TMD channel FETs. As a result, a combined transfer characteristics presented two-step drain current levels, so that their load-resistance inverter might demonstrate three value output Various functions are introduced from a unique field-effect device structure which combines or merges transition metal dichalcogenide (TMD) and InGaZnO (IGZO) channels together on one common gate: multivalue field effect transistors (FETs), photodetecting devices, and signal frequency doublers. Judging by the individual transfer characteristics of two FET devices, the n-IGZO FET always shows higher drain current and more positive-side turn-on voltage than those of n-TMD channel FETs. As a result, a combined transfer characteristic presents two-step drain current levels, so that their load-resistance inverter might demonstrate three value output voltage signals. Those ternary value inverter devices with n...

Frequency Doubler and Universal Logic Gate Based on Two-Dimensional Transition Metal Dichalcogenide Transistors with Low Power Consumption

“…Figure b displays the total current and corresponding consuming power as a function of the input voltage ( V IN ) of the complementary circuit. The lowest power measured was 10 pW at a V IN of 0.8 V, and the highest was 300 nW at a V IN of −4 V. The performance parameters of the frequency doubler based on the ambipolar transistors are summarized in Table S1 in the Supporting Information. − Our circuits show a significant improvement when compared to the tens of μW consumed by the graphene FET . In addition, an enhanced on–off current ratio and conversion gain were observed.…”

“…Figure a shows a voltage transfer curve (VTC) and the static voltage gain of the complementary circuit. The ambipolar WSe 2 FET operation (as shown in Figure e) leads to peak-to-valley type VTC characteristics with two static voltage gains (conversion gain) . Such peak-to-valley type VTC characteristics enable the complementary circuit to implement frequency doubling.…”

Quaternary NAND Logic and Complementary Ternary Inverter with p‐MoTe2/n‐MoS2 Heterostack Channel Transistors

“…Until recent years, 2D heterojunctions using transition metal dichalcogenides (TMDs) or other mono-elemental 2D semiconductors have been extensively studied, showing novel properties in respect of van der Waals (vdW) 2D junction interfaces. [1][2][3][4][5][6][7][8] Beyond PN junction diodes, other advanced device applications such as multivalue logic [9][10][11][12] and trap-induced memory [13][14][15][16][17] have also been attempted using general vdW heterojunctions. Among those applications, multivalue logic devices using 2D field-effect transistors (FETs) must be attractive in particular, casting a possibility of power reduction because conventional binary value Si-based 3D transistors nowadays face power density limit in ultralarge-scale integrated circuits.…”

Tunable Intermediate-Logic Ternary Circuits based on MoSe2-WSe2 Heterojunction

“…However, previously reported vdW-H-based ternary circuits include: (1) incomplete output voltage swing [25][26][27] and (2) narrow margin for the intermediate-logic state. [28][29][30] These issues must be addressed to make the ternary circuit suitable to practical applications. Therefore, it is necessary to investigate how to implement vdW-H-based logic more systematically.…”