Advanced gate stacks with fully silicided (FUSI) gates and high-k dielectrics. enhanced performance at reduced gate leakage

Advanced high-κ dielectric stacks with polySi and metal gates: Recent progress and current challenges

“…Device performance improvement is an ultimate goal of device scaling, and innovations in materials and device architecture are enabling it. In terms of performance, long-channel FUSI-gated HfSi x O y devices show carrier mobilities close to that of the SiO 2 control [131]. This fact combined with reduced T inv (Figures 15 and 16) results in significant drive current improvements [131].…”

“…With respect to silicide materials for FUSI gates, most of the ones explored so far are common silicides that are already in use for source/drain contacts or other microelectronics processes, such as molybdenum silicides [119,120,138], tungsten silicides [122], titanium silicides [136], hafnium silicides [134], platinum silicides [131,133], cobalt silicides [123,141] and nickel silicides [21,121,, germanides, and alloys. Nickel-based silicide materials are emerging as a leading candidate for FUSI gates for several reasons: 1) low resistivity (;15 -25 lX-cm; 2) low volume expansion (less than 20%); and 3) the fact that this material has already been introduced into Si FEOL processing for sub-90-nmtechnology nodes.…”

“…Undoped NiSi gates show a mid-gap workfunction, as evidenced, for example, from V t shift by ;0.5 V from n þ Si and p þ Si controls (Figure 15). Several techniques have been proposed to adjust the workfunction of FUSI gates toward band edges: 1) pre-doping of polySi gates with common n þ and p þ dopants before gate silicidation [126, 129-132, 135, 140, 141, 144]; 2) changing the composition of FUSI gates, in particular alloying Ni with other elements (for example, Pt or Ge for p-FET shifts and Al for n-FETs) [130,131,133,137,140]; 3) using different silicide phases [21,140,143,144];…”

Effects of interface traps and oxide traps on gate capacitance of MOS devices with ultrathin (EOT ~ 1 nm) high-κ stacked gate dielectrics

“…To improve the interface quality, typically an interfacial layer (usually oxide or oxynitride) is introduced [12]. The benefit of the interfacial layer is to take advantage of the natural Si/SiO 2 interface while also incorporating high-κ dielectrics to increase the capacitance and thickness and thereby reduce the direct tunneling probability.…”

“…The probability of bias-induced charge trapping in high-κ gate stacks is extremely high due to the large densities of "intrinsic" defects in the materials [8], [12]. The charging and discharging of these traps can greatly influence the performance of the devices and reduce the drive current due to electrostatic interaction with trapped charges [15].…”