Advanced Chip Last Process Integration for Fan Out WLP

Yoo, Taewon; Lee, Seok Hyun; Suk, Kyoung Lim; Kim, Eung Kyu; Choi, Wooseok; Kim, Dae Woo; Kim, Dong Wook

doi:10.1109/ectc51906.2022.00220

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Cited by 4 publications

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“…FOPLP is an extension of wafer-level fan-out that has a larger substrate size of about 600 mm compared to that of FOWLP, which is about 300 mm. This increases the throughput and lowers the cost-per-device margin compared with FOWLP [ 6 ].…”

Section: Introductionmentioning

confidence: 99%

Modern Trends in Microelectronics Packaging Reliability Testing

Bender,

Bernstein,

Boning

2024

Micromachines

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In this review, recent trends in microelectronics packaging reliability are summarized. We review the technology from early packaging concepts, including wire bond and BGA, to advanced techniques used in HI schemes such as 3D stacking, interposers, fan-out packaging, and more recently developed silicon interconnect fabric integration. This review includes approaches for both design modification studies and packaged device validation. Methods are explored for compatibility in new complex packaging assemblies. Suggestions are proposed for optimizations of the testing practices to account for the challenges anticipated in upcoming HI packaging schemes.

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Section: Introductionmentioning

confidence: 99%